Patents by Inventor Seong Kwang Kim

Seong Kwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220204502
    Abstract: The present invention relates to a novel crystal polymorphism of a P13K inhibitor, and a method for preparing same. The novel crystal form of the present invention has remarkably superior non-hygroscopicity, can exhibit a superior pharmacological effect due to high blood levels, and exhibits high bioavailability, and thus is suitable for pharmaceutical formulations.
    Type: Application
    Filed: May 8, 2020
    Publication date: June 30, 2022
    Inventors: Seong Heon KIM, Joon Kwang LEE, Yong Ho SUN, Ji Han KIM
  • Publication number: 20210328765
    Abstract: A method for encryption according to an embodiment includes generating a ciphertext for a secret key that is an integer vector by using an integer-based first homomorphic encryption algorithm, generating a key stream that is the integer vector from a nonce and the secret key by using a key stream generator, encoding the key stream by using a message encoding function of the first homomorphic encryption algorithm, encoding a message that is a real vector by using a message encoding function of a real number-based second homomorphic encryption algorithm, generating a ciphertext for the message by using a result of the encoding of the key stream and a result of the encoding of the message, and transmitting the nonce, the ciphertext for the secret key, and the ciphertext for the message to an apparatus for converting a ciphertext.
    Type: Application
    Filed: October 27, 2020
    Publication date: October 21, 2021
    Inventors: Joo Hee LEE, Duk Jae MOON, Hyo Jin YOON, Ji Hoon CHO, Eun Kyung KIM, Seong Kwang KIM, Joo Young LEE, Jin Cheol HA, Won Seok CHOI
  • Publication number: 20210175262
    Abstract: Various embodiments relate to a stackable 3D artificial neural network device and a manufacturing method thereof. According to various embodiments, a device is manufactured to include a substrate, a neuron block placed on some areas on one side of the substrate, a synapse block placed on the rest of the areas on one side of the substrate, and the neuron block and the synapse block may include at least one first channel element arranged on one side of the substrate and at least one second channel element stacked on the first channel element.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 10, 2021
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Sanghyeon Kim, Seong Kwang Kim
  • Patent number: 10886161
    Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: January 5, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyung-jun Kim, Sanghyeon Kim, Hansung Kim, Seong Kwang Kim, Hyeong Rak Lim
  • Publication number: 20190287846
    Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.
    Type: Application
    Filed: February 22, 2019
    Publication date: September 19, 2019
    Inventors: Hyung-jun KIM, Sanghyeon KIM, Hansung KIM, Seong Kwang KIM, Hyeong Rak LIM
  • Patent number: 9941168
    Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 10, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sanghyeon Kim, Hyung-jun Kim, Jae-Phil Shim, Seong Kwang Kim, Won Jun Choi
  • Publication number: 20180082900
    Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.
    Type: Application
    Filed: June 23, 2017
    Publication date: March 22, 2018
    Inventors: Sanghyeon KIM, Hyung-jun KIM, Jae-Phil SHIM, Seong Kwang KIM, Won Jun CHOI
  • Publication number: 20070158815
    Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
    Type: Application
    Filed: April 2, 2004
    Publication date: July 12, 2007
    Inventors: Fung Chen, Seong Kwang Kim, Wee Cha, Yi-Sheng Sun, Wolfgang Hetzel, Jochen Thomas