Patents by Inventor Seong-Soon Cho
Seong-Soon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105604Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 11854975Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: GrantFiled: August 27, 2021Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Publication number: 20230127052Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: ApplicationFiled: December 16, 2022Publication date: April 27, 2023Inventors: TAEKYUNG KIM, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
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Patent number: 11545503Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: GrantFiled: January 21, 2020Date of Patent: January 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
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Publication number: 20220328520Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Patent number: 11374019Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: GrantFiled: April 1, 2020Date of Patent: June 28, 2022Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Patent number: 11289034Abstract: A display device includes a backlight unit including light source rows, each of the light source rows including light source blocks, a display panel configured to display an image by transmitting light emitted by the backlight unit, a panel driver configured to drive the display panel, and a backlight driver configured to drive the backlight unit. The backlight driver is configured to perform a vertical direction scan operation that sequentially select the light source rows and a horizontal direction sequential driving operation that sequentially drives the light source blocks included in a selected light source row of the light source rows.Type: GrantFiled: January 27, 2020Date of Patent: March 29, 2022Inventors: Jahun Koo, Seong Soon Cho, Jongwoon Kim, Kyung-Hun Lee
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Publication number: 20210391260Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 11107765Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: GrantFiled: April 21, 2020Date of Patent: August 31, 2021Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Publication number: 20210035507Abstract: A display device includes a backlight unit including light source rows, each of the light source rows including light source blocks, a display panel configured to display an image by transmitting light emitted by the backlight unit, a panel driver configured to drive the display panel, and a backlight driver configured to drive the backlight unit. The backlight driver is configured to perform a vertical direction scan operation that sequentially select the light source rows and a horizontal direction sequential driving operation that sequentially drives the light source blocks included in a selected light source row of the light source rows.Type: ApplicationFiled: January 27, 2020Publication date: February 4, 2021Inventors: Jahun KOO, Seong Soon CHO, Jongwoon KIM, Kyung-Hun LEE
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Patent number: 10878901Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: March 29, 2019Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joonhee Lee, Jiyoung Kim, Jintaek Park, Seong Soon Cho
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Patent number: 10840183Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.Type: GrantFiled: April 16, 2020Date of Patent: November 17, 2020Inventors: Seok-Jung Yun, Sung-Hun Lee, Jee-Hoon Han, Yong-Won Chung, Seong Soon Cho
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Patent number: 10790294Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.Type: GrantFiled: March 21, 2017Date of Patent: September 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Joo Shim, Seong Soon Cho, Ji Hye Kim, Kyung Jun Shin
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Publication number: 20200251417Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Publication number: 20200243445Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.Type: ApplicationFiled: April 16, 2020Publication date: July 30, 2020Inventors: Seok-Jung YUN, Sung-Hun LEE, Jee-Hoon HAN, Yong-Won CHUNG, Seong Soon CHO
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Publication number: 20200227438Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: ApplicationFiled: April 1, 2020Publication date: July 16, 2020Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Publication number: 20200152643Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: ApplicationFiled: January 21, 2020Publication date: May 14, 2020Inventors: TAEKYUNG KIM, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
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Patent number: 10644023Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: GrantFiled: June 26, 2018Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Patent number: 10541248Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: GrantFiled: July 26, 2018Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
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Patent number: 10461030Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.Type: GrantFiled: October 21, 2016Date of Patent: October 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Young-Ho Lee, Seong-Soon Cho, Woon-Kyung Lee