Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.

Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.

Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.

Abstract: A dispenser arrangement for fluidic dispensing control into a microfluidic component comprising an enclosed fluid holding area having a base portion and a top portion and a valve adapted to be movable between an open position and a closed position and positioned at least partially in the fluid holding area. The valve comprises an elongated hollow portion having a body and two ends adapted for fluid flow from the fluid holding area to the microfluidic component in the open position, a first opening on the body of the hollow portion positioned within the fluid holding area allowing fluid communication from the fluid holding area to the microfluidic component in the open position, a sealing portion connected to a first end of the hollow portion positioned within the fluid holding area adapted for sealing connection with the top portion of the fluid holding area in the closed position and a slant second opening at a second end of the hollow portion positioned outside of the fluid holding area.

Abstract: A dispenser arrangement for fluidic dispensing control into a microfluidic component comprising an enclosed fluid holding area having a base portion and a top portion and a valve adapted to be movable between an open position and a closed position and positioned at least partially in the fluid holding area. The valve comprises an elongated hollow portion having a body and two ends adapted for fluid flow from the fluid holding area to the microfluidic component in the open position, a first opening on the body of the hollow portion positioned within the fluid holding area allowing fluid communication from the fluid holding area to the microfluidic component in the open position, a sealing portion connected to a first end of the hollow portion positioned within the fluid holding area adapted for sealing connection with the top portion of the fluid holding area in the closed position and a slant second opening at a second end of the hollow portion positioned outside of the fluid holding area.

Abstract: A sensor array integrated electrochemical chip is provided wherein the chip has an array of electrodes. The array may be formed on a base plate bonded to a cover plate having an opening. The opening can be a window or a depression. The plates are bounded such that they define a cavity, with the array being within the cavity. Conducting lines for connecting the electrodes to electrochemical instruments may be formed on the same surface of the base plate on which the electrodes are formed. At least one of the electrodes may be covered by a coating doped with a ferrocene compound. The coating may be a supported bilayer lipid membrane doped with benzoylferrocene. The doped ferrocene compound may be oxidized.

Abstract: A microfluidics package (1) comprising a substrate (6) having a top surface, said top surface comprises at least one fluid channel (11, 12), at least one fluidic chip (2) having a top surface, a bottom surface, at least one side surface, and at least one passage to allow a fluid to traverse from the top surface or any side surface to the bottom surface of the chip; sides are adhesive, wherein the first adhesive side of the sheet (4) is secured to the substrate (6), and the at least one fluidic chip (2) is secured by the second adhesive side of the sheet (4), said fluidic chip (2) being arranged such that the at least one passage of the fluidic chip is in fluid communication with the at least one fluid channel (11, 12) of the substrate.