Abstract: The present disclosure relates to a temporary wafer bonding process including the steps of: providing a wafer for back processing by laminating a plain protective film on a front surface of the wafer; providing a rigid carrier; bonding the rigid carrier to the plain protective film by the intermediate of a bonding material layer; processing a back surface of the wafer; and separating the rigid carrier and the plain protective film from the wafer.

Abstract: A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T1 and setting the pressure of the environment to a value P1, contacting the surface with a fluid having a solidifying temperature at the pressure value P1 above the value T1 and having a vaporizing temperature at the pressure value P1 below 80° C., thereby solidifying the fluid in pores of the material, thereby sealing the pores, treating the surface, wherein the treatment is preferably an etching or a modification of the surface, and setting the temperature of the surface to a value T2 and setting the pressure of the environment to a value P2 in such a way as to vaporize the fluid.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Abstract: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C., thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.

Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C, thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.

Abstract: The present invention discloses the formation of a hard mask layer in an organic polymer layer by modifying at least locally the chemical composition of a part of said exposed organic low-k polymer. This modification starts from an exposed surface of the polymer and extends into the polymer thereby increasing the chemical resistance of the modified part of the polymer. As a result, this modified part can be used as a hard mask or an etch stop layer for plasma etching.

Abstract: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: In a method of removal of silicon carbide layers, and in particular amorphous SiC on a substrate, the exposed part of a carbide-silicon layer is at least partly converted into an oxide-silicon layer or a nitride silicon layer by exposing the carbide-silicon layer to an oxygen-containing plasma or a nitrogen-containing plasma. In a separate step, the oxide-silicon or nitride-silicon layer is then removed from the substrate. An oxygen containing plasma can be a reactive ion etch plasma, a chemical vapor deposition plasma, or a plasma afterglow. In certain embodiments, the substrate can be a component of an integrated circuit, or a component of a MEMS device.

Abstract: This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.

Abstract: This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.

Abstract: This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.