Patents by Inventor Sergio Lecce

Sergio Lecce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170188419
    Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.
    Type: Application
    Filed: July 21, 2016
    Publication date: June 29, 2017
    Inventors: Manuel Gaertner, Sergio Lecce, Giovanni Luca Torrisi
  • Patent number: 9595947
    Abstract: A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: March 14, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vanni Poletto, Patrizia Milazzo, Sergio Lecce
  • Publication number: 20160094210
    Abstract: A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.
    Type: Application
    Filed: July 13, 2015
    Publication date: March 31, 2016
    Inventors: Vanni POLETTO, Patrizia MILAZZO, Sergio LECCE
  • Publication number: 20160094022
    Abstract: A fail-safe device may be coupled to a main device for actuating a switch responsive to a failure. The fail-safe device may include a fail-safe circuit, and an isolation trench surrounding the fail-safe circuit and isolating the fail-safe circuit from the main device. The fail-safe device may include an internal power supply connection, an internal reference voltage connection, a self-biased drive block configured to drive the at least one switch, and a receiver configured to receive failure signals from the main device.
    Type: Application
    Filed: June 29, 2015
    Publication date: March 31, 2016
    Inventors: Vanni POLETTO, Manuel Gaertner, Sergio Lecce, Giovanni Luca Torrisi
  • Publication number: 20150208557
    Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 23, 2015
    Inventors: Domenico Massimo PORTO, Giovanni Luca TORRISI, Sergio LECCE, Manuel GAERTNER
  • Patent number: 8907652
    Abstract: A generator of a voltage logarithmically variable with temperature may include a differential amplifier having a pair of transistors, each coupled with a respective bias network adapted to bias in a conduction state the transistors first and second respectively with a constant current and with a current proportional to the working absolute temperature. The pair of transistors may generate between their control nodes the voltage logarithmically variable with temperature. The differential amplifier may have a common bias current generator coupled between the common terminal of the differential pair of transistors and a node at a reference potential, and a feedback line to provide a path for the current difference between the sum of currents flowing through the transistors of the differential pair and the common bias current.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Sergio Lecce, Maurizio Rossi
  • Publication number: 20120256605
    Abstract: A generator of a voltage logarithmically variable with temperature may include a differential amplifier having a pair of transistors, each coupled with a respective bias network adapted to bias in a conduction state the transistors first and second respectively with a constant current and with a current proportional to the working absolute temperature. The pair of transistors may generate between their control nodes the voltage logarithmically variable with temperature. The differential amplifier may have a common bias current generator coupled between the common terminal of the differential pair of transistors and a node at a reference potential, and a feedback line to provide a path for the current difference between the sum of currents flowing through the transistors of the differential pair and the common bias current.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 11, 2012
    Applicant: STMicroelectronics S.r.I.
    Inventors: Sergio Lecce, Maurizio Rossi
  • Patent number: 6215338
    Abstract: Relatively low currents are monitored through an integrated DMOS power transistor in a low-side driver configuration. A feedback circuit is responsive to the voltage applied to a gate of the DMOS power transistor to limit the minimum value to which the drain-source voltage may drop to keep it sufficiently high, and to allow a reliable monitoring of the current through the power transistor, even at relatively low levels. This is performed by increasing the conduction resistance of the power transistor at low current levels.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: April 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luigi Gervasi, Sergio Lecce, Franco Cocetta, Mauro Merlo
  • Patent number: 6072359
    Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2).
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: June 6, 2000
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Davide Brambilla, Daniela Nebuloni, Giorgio Rossi, Sergio Lecce
  • Patent number: 5917254
    Abstract: A circuit for the controlled recycle without oscillation of a discharge current from an inductive load. The circuit comprises an active element connected, in series with the inductive load, between first and second power supply terminals, and having a control terminal to which a driver circuit is connected. The circuit further includes a recycling regulating circuitry connected to a connection node between the active element and the inductive load, and sensitive to a voltage threshold at the connection node to generate, depending on attainment of that threshold, a power-on signal for application to the control terminal effective to start up recycling of the discharge current through the active element. The circuit further comprises a control circuit for controlling the voltage oscillation at the connection node at the end of the recycling.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: June 29, 1999
    Assignee: SGS-Thomson Microelectronics,S.r.l.
    Inventors: Sergio Lecce, Massimo Grasso, Giorgio Rossi
  • Patent number: 5874852
    Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2).
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: February 23, 1999
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Davide Brambilla, Daniela Nebuloni, Giorgio Rossi, Sergio Lecce