Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: A high-voltage resistor integrated on a semiconductor substrate with opposite sign conductivity, and being of a type with one end connected to the substrate and another end connected to a lower electric potential than the substrate, further comprises at least one thin layer of the field plate type covering at least a section of the resistor.

Abstract: An integrated structure is described, that comprises a vertical bipolar transistor and a vertical MOSFET transistor, where, in order to reduce the series resistance of the MOSFET transistor, the collector region of the bipolar transistor and the drain region of the MOSFET transistor are both parts of a common zone and are contiguous each other, so that the high charge injection in the collector region when the bipolar transistor is in conduction state, causes a simultaneous increase in the conductivity of the drain region of the MOSFET transistor.Both transistors are formed by cells each containing an elementary bipolar transistor and an elementary MOSFET transistor.

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold is formed on a chip of an N-type semiconductor material and includes a plurality of isolated N-type regions. Each isolated N-type region is bounded laterally by an isolating region and at the bottom by buried P-type and N-type regions which form in combination a junction with a predetermined reverse conduction threshold and means of connecting the junctions of the various isolated regions serially together. The buried N-type region of the first junction in the series is connected to a common electrode, which also is one terminal of the device, over an internal path of the N-type material of the chip, and the buried P-type region of the last junction in the series contains an additional buried N-type region which is connected electrically to a second terminal of the device.

Abstract: A spiral resistor being of a type formed on a semiconductor substrate to withstand high voltages, comprises at least one thin field-plate layer covering said substrate between adjacent turns of the resistor. This prevents the well-known phenomenon of the "phantom gate" from occurring which would result in the characteristics of spiral resistors deteriorating over time.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.

Abstract: A driving circuit is provided for a power transistor connected to an inductive load. A detection resistor is placed between ground and the emitter of the power transistor. The driving circuit has a first portion which is capable of generating a first current which is a non-linear function of the voltage across the detection resistance. A second portion of the driving circuit is used to generate a base current for the power transistor that is proportional to the first current. The non-linear function of the first current compensates for the non-linear gain with respect to collector current of the power transistor.

Abstract: A control circuit for slowly turning off a solid-state power transistor, particularly for inductive loads, comprising means for limiting the load current flowing through the switch, and timing and control circuits to ensure, irrespective of the duration of a command pulse, slowed turn-off of the switch with a predetermined delay as to the time when the maximum load current value is reached, thereby keeping the power dissipation through the switch during the load current limiting phase within predetermined values and the turn-off overvoltage within predetermined levels.

Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.

Abstract: A circuit for connecting a first circuit node to either a second or a third circuit node relative to the voltage potential on the third circuit node includes two bipolar transistors connected in series. The collectors of both transistors are connected to the first circuit node. The emitter of the first transistor is connected to the second circuit node and the emitter of the second transistor is connected to the third circuit node. Means are provided for maintaining the base of the second transistor at a constant, preset bias voltage.

Abstract: A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).

Abstract: A monolithic vertical-type semiconductor power device comprises an N+ type substrate 1 over which there is superimposed an N- type epitaxial layer 2 in which there is obtained a P type isolation pocket 3. The pocket 3 contains N type regions 4, 15 and P type regions 6 which in turn contain N+ type regions 11, 12 and P type regions 7, 9, 10 which define circuit components of the device. Isolation pocket 3 is wholly covered by a first metallisation 21 connect to ground. The metallisation 21 is in turn protected by a layer of insulating material 18 suitable for allowing the crossing of metal tracks or of a second metallisation for the connection of the different components.

Abstract: Circuits are provided for protecting against negative overvoltages of a power supply in an integrated circuit including a power device (P). The protection circuits include a voltage limiting device (T4) interposed between supply and control terminals of the power device, as well as a switching device (T6). The switching device is interposed between a control terminal of the voltage limiting means and ground. The switching means is controlled by the power supply to cause conduction of the voltage limiting means for firing the power device if a positive overvoltage on the supply terminal (CL) of the power device is combined with a negative overvoltage of the power supply (Vb). In some embodiments the switching device and the voltage limiting device are both NPN transistors. In other embodiments the the switching device and the voltage limiting device are both MOS transistors.

Abstract: A limiting circuit comprises a comparator (B), which makes a comparison between the output voltage (Vc) of a power device and a predetermined reference voltage (Vrif). In the case wherein the output voltage is just below the reference voltage, the comparator supplies a current to the load (L) suitable for preventing the output voltage from falling further below the reference voltage.

Abstract: The device for protection against the short circuit of an MOS-type power device comprises at least one secondary branch cirucit arranged in parallel with a main branch circuit which includes the power transistor. The secondary branch includes a control MOS transistor having the same characteristics as the power transistor under control and the ability to conduct a current equal to a fraction of that flowing through the power transistor. The gate of the control transistor is connected directly with that of the power transistor. The secondary branch also includes means sensitive to temperature which, in the case of a current flow corresponding to the short circuit current of the power transistor, act on the gate common to the control and to the power transistors so as to lower its voltage and thus limit the conduction of same.

Abstract: A circuit for detecting the current in an MOS type power transistor comprises a detection transistor (T2) connected with its drain and gate in common to the power transistor (T1) and having characteristics such that the current flowing through it is equal to a fraction of the current (I1) flowing through the power transistor (T1). Downstream from the detection transistor (T2) is a comparison transistor (T6, T13) for comparing a first current (I3), which is equal to a fraction of the current flowing through the detection transistor, with a second or reference current (Ig1) having a pre-set value. The comparison transistor (T6, T13) produces a detection signal of the value of the current in the power transistor (I1) in relation to the difference between the first current (I3) and the reference current (Ig1).

Abstract: The circuit switches the power supply of the integrated circuit over to the input voltage of the switching regulator during the initial starting phase, and over to the output of said regulator once the steady state has been reached.

Abstract: The generator of drive signals comprises a ramp generator suitable for receiving a square waveform input signal and for converting it into an output signal variable between a lower level and an upper level with upward and downward ramps having a preset slope, a first comparator with a non-inverting input connected to the output of said ramp generator and an inverting input connected to a first reference signal source and a second comparator with an inverting input connected to the output of said ramp generator and a non-inverting input connected to a second reference signal source.

Abstract: A monolithic integrated circuit (M) includes a power device (Q3, Q4) for driving an inductive load (L) and a control device for the power device. The control device comprises a voltage limiting circuit which includes a first transistor (Q2) responsive to negative impulses of the supply voltage and a second transistor (Q5) which is controlled by the first transistor for controlling re-firing of the power device in case of a negative pulse of the power voltage during a quenching period of the power device. The monolithic integrated circuit includes a substrate (5) having a substrate surface forming a supply voltage terminal of the power device and having a substrate voltage. An annular pocket (40) is formed in the substrate to surround or at least partially contain at least the first transistor (Q2) of the voltage limiting circuit.