Patents by Inventor Sergio Schuler

Sergio Schuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10521395
    Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 31, 2019
    Assignee: Mythic, Inc.
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Patent number: 8832702
    Abstract: A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: September 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Klas M. Bruce, Sergio Schuler, Matt B. Smittle, Michael D. Snyder, Gary L. Whisenhunt
  • Patent number: 7805581
    Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael D. Snyder, David C. Holloway, Trinh H. Nguyen, Sergio Schuler, Gary L. Whisenhunt
  • Patent number: 7681021
    Abstract: A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: March 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergio Schuler, Michael D. Snyder, Leick D. Robinson, David M. Thompson
  • Publication number: 20090249048
    Abstract: A data processing system includes a branch target buffer (BTB) including a plurality of entries, each entry comprising a tag portion and a long branch indicator. The system also includes segment target address storage circuitry which stores a plurality of segment target addresses, index storage circuitry which stores a plurality of indices for indexing into the segment target address storage circuitry, and control circuitry which receives an instruction address and determines whether the instruction address matches a valid entry in the BTB. When the instruction address matches a valid entry in the BTB and the long branch indicator of the valid entry indicates a long branch, the index storage circuitry provides a selected index of the plurality of indices selected by the received instruction address. In response to the selected index, the segment target address storage circuitry provides a selected segment target address as a higher order target address portion.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Sergio Schuler, Stephen R. Shannon, Michael D. Snyder
  • Publication number: 20080282251
    Abstract: A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Klas M. Bruce, Sergio Schuler, Matt B. Smittle, Michael D. Snyder, Gary L. Whisenhunt
  • Publication number: 20080209182
    Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 28, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael D. Snyder, David C. Holloway, Trinh H. Nguyen, Sergio Schuler, Gary L. Whisenhunt
  • Publication number: 20080082843
    Abstract: A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventors: Sergio Schuler, Michael D. Snyder, Leick D. Robinson, David M. Thompson