Patents by Inventor Seshadri Ganguli

Seshadri Ganguli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220165852
    Abstract: A method of filling a feature in a semiconductor structure includes forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD); wherein the barrier layer is one of cobalt (Co), molybdenum (Mo), molybdenum nitride (MoN) plus Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN); and forming a metal layer in the feature and over the barrier layer by one of ALD or CVD; wherein the metal layer is one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W).
    Type: Application
    Filed: November 18, 2021
    Publication date: May 26, 2022
    Inventors: Srinivas GANDIKOTA, Yixiong YANG, Jacqueline S. WRENCH, Luping LI, Yong YANG, Seshadri GANGULI
  • Publication number: 20220122923
    Abstract: Embodiments of the disclosure relate to methods and materials for forming barrier layers with enhanced barrier performance and/or reduced via resistance. Some embodiments of the disclosure provide methods for passivating a metal surface by exposing the metal surface to a metal complex comprising an organic ligand with at least three carbon atoms and a double or triple bond that eta bonds with a central metal atom. Some embodiments provide barrier layers within vias which enable a reduction in resistance of at least 25% as a result of thinner barrier layers with equivalent barrier properties.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Lu Chen, Seshadri Ganguli, Sang Ho Yu, Feng Chen
  • Publication number: 20220108916
    Abstract: A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).
    Type: Application
    Filed: September 30, 2021
    Publication date: April 7, 2022
    Inventors: Yixiong YANG, Seshadri GANGULI, Srinivas GANDIKOTA, Yong YANG, Jacqueline S. WRENCH, Luping LI
  • Patent number: 11282745
    Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: March 22, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sang-Ho Yu, Seshadri Ganguli
  • Publication number: 20220068935
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Patent number: 11171141
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20210320064
    Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: SUKETU A. PARIKH, RONG TAO, ROEY SHAVIV, JOUNG JOO LEE, SESHADRI GANGULI, SHIRISH PETHE, DAVID GAGE, JIANSHE TANG, MICHAEL A STOLFI
  • Publication number: 20210285102
    Abstract: Methods of depositing a metal film are discussed. A metal film is formed on the bottom of feature having a metal bottom and dielectric sidewalls. Formation of the metal film comprises exposure to a metal precursor and an alkyl halide catalyst while the substrate is maintained at a deposition temperature. The metal precursor has a decomposition temperature above the deposition temperature. The alkyl halide comprises carbon and halogen, and the halogen comprises bromine or iodine.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Liqi Wu, Joung Joo Lee, Kai Wu, Xi Cen, Wei Lei, Sang Ho Yu, Seshadri Ganguli
  • Patent number: 11075165
    Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 27, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Suketu A Parikh, Rong Tao, Roey Shaviv, Joung Joo Lee, Seshadri Ganguli, Shirish Pethe, David Gage, Jianshe Tang, Michael A Stolfi
  • Publication number: 20210214842
    Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 15, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Seshadri Ganguli, Xi Cen
  • Patent number: 11060188
    Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 13, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sang Ho Yu, Seshadri Ganguli
  • Patent number: 10930550
    Abstract: Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Seshadri Ganguli, Sang Ho Yu, Lu Chen
  • Publication number: 20210020569
    Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Inventors: SUKETU A. PARIKH, RONG TAO, ROEY SHAVIV, JOUNG JOO LEE, SESHADRI GANGULI, SHIRISH PETHE, DAVID GAGE, JIANSHE TANG, MICHAEL A. STOLFI
  • Publication number: 20200350204
    Abstract: Methods for selectively depositing on non-metallic surfaces are disclosed. Some embodiments of the disclosure utilize an unsaturated hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked non-metallic surfaces. Some embodiments of the disclosure relate to methods of forming metallic vias with decreased resistance.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 5, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Sang Ho Yu, Lu Chen, Seshadri Ganguli
  • Publication number: 20200343136
    Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.
    Type: Application
    Filed: April 28, 2019
    Publication date: October 29, 2020
    Inventors: SANG-HO YU, SESHADRI GANGULI
  • Publication number: 20200286897
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 10, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Patent number: 10608097
    Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Seshadri Ganguli, Shih Chung Chen, Rajesh Sathiyanarayanan, Atashi Basu, Lin Dong, Naomi Yoshida, Sang Ho Yu, Liqi Wu
  • Publication number: 20200090991
    Abstract: Methods for forming barrier/seed layers for interconnect structures are provided. More specifically, methods of depositing a film on a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall with a dielectric surface and a bottom with a conductive surface. A manganese-ruthenium film is formed in the opening in the first surface of the substrate on the conductive surface.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 19, 2020
    Inventors: Sang Ho Yu, Seshadri Ganguli
  • Publication number: 20200063263
    Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 27, 2020
    Inventors: Yixiong Yang, Wei V. Tang, Seshadri Ganguli, Sang Ho Yu, Feng Q. Liu, Jeffrey W. Anthis, David Thompson, Jacqueline S. Wrench, Naomi Yoshida
  • Publication number: 20190390340
    Abstract: Methods of depositing a metal film with high purity are discussed. Some embodiments utilize a thermal ALD process comprising an alkyl halide and a metal precursor. Some embodiments selectively deposit a metal film with high purity on a metal surface over a dielectric surface. Some embodiments selectively deposit a metal film with high purity on a dielectric surface over a metal surface. Some embodiments deposit a metal film with greater than 99% metal atoms on an atomic basis.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Inventors: Sang Ho Yu, Seshadri Ganguli, Byunghoon Yoon, Wei Min Chen