Abstract: A curing tool for fabricating solar cells using UV-curing of light-receiving surfaces of the solar cells, and the resulting solar cells, are described herein. In an example, a curing tool combines a UV-exposure stage and one or more of a deposition or an annealing stage to fabricate a solar cell. For example, a radiation curing stage can precede a back end processing stage used to perform operations on a back contact solar cell. The curing tool can therefore be used to perform a method to improve UV stability of solar cells.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.

Abstract: Methods of passivating light-receiving surfaces of solar cells with high energy gap (Eg) materials, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A Group III-nitride material layer is disposed above the passivating dielectric layer. In another example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A large direct band gap material layer is disposed above the passivating dielectric layer, the large direct band gap material layer having an energy gap (Eg) of at least approximately 3.3. An anti-reflective coating (ARC) layer disposed on the large direct band gap material layer, the ARC layer comprising a material different from the large direct band gap material layer.

Abstract: One embodiment relates to a method of fabricating a solar cell. A silicon lamina is cleaved from the silicon substrate. The backside of the silicon lamina includes the P-type and N-type doped regions. A metal foil is attached to the backside of the silicon lamina. The metal foil may be used advantageously as a built-in carrier for handling the silicon lamina during processing of a frontside of the silicon lamina. Another embodiment relates to a solar cell that includes a silicon lamina having P-type and N-type doped regions on the backside. A metal foil is adhered to the backside of the lamina, and there are contacts formed between the metal foil and the doped regions. Other embodiments, aspects and features are also disclosed.

Abstract: Methods of passivating light-receiving surfaces of solar cells with high energy gap (Eg) materials, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A Group III-nitride material layer is disposed above the passivating dielectric layer. In another example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A large direct band gap material layer is disposed above the passivating dielectric layer, the large direct band gap material layer having an energy gap (Eg) of at least approximately 3.3. An anti-reflective coating (ARC) layer disposed on the large direct band gap material layer, the ARC layer comprising a material different from the large direct band gap material layer.

Abstract: One embodiment relates to a method of fabricating a solar cell. A silicon lamina is cleaved from the silicon substrate. The backside of the silicon lamina includes the P-type and N-type doped regions. A metal foil is attached to the backside of the silicon lamina. The metal foil may be used advantageously as a built-in carrier for handling the silicon lamina during processing of a frontside of the silicon lamina. Another embodiment relates to a solar cell that includes a silicon lamina having P-type and N-type doped regions on the backside. A metal foil is adhered to the backside of the lamina, and there are contacts formed between the metal foil and the doped regions. Other embodiments, aspects and features are also disclosed.

Abstract: The present disclosure provides improved approaches for marking and individual tracking of solar cells. These approaches can be used to identify key manufacturing process steps requiring optimization and/or significant factors extending solar cell lifetime. The approaches described herein for marking and individual tracking of solar cells avoid or greatly minimize any negative impact on solar cell performance while improving quality control of solar cells across multiple manufacturing steps and throughout the entire solar cell lifecycle. Embodiments described herein include a solar cell comprising a substrate having a front side and a back side. The substrate comprises at least one diffusion region of a first polarity. A first set of conductive conduits in the first set is electrically coupled to at least one active diffusion region of a first polarity. The solar cell further comprises a marking above an inactive region of the substrate.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact layer, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A P-type emitter region is disposed on the back surface of the substrate. An N-type emitter region is disposed in a trench formed in the back surface of the substrate. An N-type passivation layer is disposed on the N-type emitter region. A first conductive contact structure is electrically connected to the P-type emitter region. A second conductive contact structure is electrically connected to the N-type emitter region and is in direct contact with the N-type passivation layer.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: Methods of fabricating solar cells using simplified deposition processes, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell involves loading a template substrate into a deposition chamber and, without removing the template substrate from the deposition chamber, performing a deposition method. The deposition method involves forming a first silicon layer on the template substrate, the first silicon layer of a first conductivity type. The deposition method also involves forming a second silicon layer on the first silicon layer, the second silicon layer of the first conductivity type. The deposition method also involves forming a third silicon layer above the second silicon layer, the third silicon layer of a second conductivity type. The deposition method also involves forming a solid state doping layer on the third silicon layer, the solid state doping layer of the first conductivity type.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact layer, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A P-type emitter region is disposed on the back surface of the substrate. An N-type emitter region is disposed in a trench formed in the back surface of the substrate. An N-type passivation layer is disposed on the N-type emitter region. A first conductive contact structure is electrically connected to the P-type emitter region. A second conductive contact structure is electrically connected to the N-type emitter region and is in direct contact with the N-type passivation layer.

Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: Solar cells having epitaxial passivation layers are described. In an example, a solar cell includes a crystalline substrate. An epitaxial passivation layer is disposed directly on the crystalline substrate. A plurality of alternating N-type and P-type emitter regions is disposed on the epitaxial passivation layer.

Abstract: Methods of fabricating solar cells having passivation layers, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a first surface and a second surface. A plurality of emitter regions is disposed on the first surface of the substrate and spaced apart from one another. An amorphous silicon passivation layer is disposed on each of the plurality of emitter regions and between each of the plurality of emitter regions, directly on an exposed portion of the first surface of the substrate.