Abstract: Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.

Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.

Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.

Abstract: The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the device for controlling a setup/hold time of an input signal can provide a technique which can optimize the setup/hold time at a small cost in comparison with a physical metal option control system.

Abstract: A semiconductor memory device has an over-driving scheme through which it is possible to perform effective over-driving regardless of the fluctuation of manufacturing and driving environment. The semiconductor memory device includes a first power supplying block for providing a normal voltage, a first driving block for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying block, a second driving block for driving the connection node with a voltage higher than the normal voltage, and a control block for generating an over-driving control signal which controls the second driving block by detecting a level of the voltage on the connection node to that of a preset reference voltage.

Abstract: A semiconductor memory device has an over-driving scheme through which it is possible to perform effective over-driving regardless of the fluctuation of manufacturing and driving environment. The semiconductor memory device includes a first power supplying block for providing a normal voltage, a first driving block for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying block, a second driving block for driving the connection node with a voltage higher than the normal voltage, and a control block for generating an over-driving control signal which controls the second driving block by detecting a level of the voltage on the connection node to that of a preset reference voltage.

Abstract: The present invention generally relates to setup/hold time control devices, and more specifically, to a setup/hold time control device which can change setup/hold time of various control signals applied from an input buffer by software operation commands. The setup/hold time control device of the present invention comprises transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the present invention can provide a technique which can optimize the setup/hold time with small cost in comparison with a physical metal option control system.