Patents by Inventor Seung-Sik Park
Seung-Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964636Abstract: A method of controlling an air blowing apparatus includes: determining whether there is precipitation through a rain sensor by a controller; determining whether the air blowing apparatus is in an automatic mode in a precipitation condition by the controller; determining a vehicle speed when the air blowing apparatus is in the automatic mode in the precipitation condition; and setting power and a spray angle of the air blowing apparatus by comparing a rainfall received from the rain sensor to a stored rainfall by the controller. Setting the power and the spray angle of the air blowing apparatus includes compensating the spray angle and a spray amount by measuring a flow speed and a flow angle of rainwater through the rain sensor by the controller.Type: GrantFiled: June 28, 2023Date of Patent: April 23, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Jong Min Park, Seung Sik Han, Ki Hong Lee, Nak Kyoung Kong
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Patent number: 11963403Abstract: A display device includes a first substrate. A transistor is disposed on the first substrate. A light-emitting element is connected to the transistor. An insulating layer is disposed between the transistor and the light-emitting element. A second substrate at least partially overlaps the first substrate. A color conversion layer is disposed on the second substrate. The insulating layer includes a first insulating layer and a second insulating layer. A distance between the first insulating layer and the first substrate is less than a distance between the second insulating layer and the first substrate. The first insulating layer includes a light blocking material.Type: GrantFiled: August 13, 2019Date of Patent: April 16, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seung Hyun Park, Joo Sun Yoon, Woo Sik Jun, Yun-Mo Chung
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Patent number: 11938232Abstract: The present invention relates to an X-ray irradiator for single blood bags, comprising: an X-ray irradiator main body provided with a chamber configured to safely hold a single blood bag therein and an X-ray tube configured to irradiate the chamber with X-rays; a loading part configured to load the blood bag; and a transfer part configured to transfer the blood bag between the loading part and the chamber to which X-rays are to be emitted. The X-ray irradiator for single blood bags according to the present invention can treat a single blood bag with X-rays, such that treatment optimized for a small amount of a blood bag can be performed, and a system configuration can be simplified by using an X-ray tube.Type: GrantFiled: December 17, 2019Date of Patent: March 26, 2024Assignee: KOREA INSTITUTE OF RADIOLOGICAL & MEDICAL SCIENCESInventors: Seung Woo Park, Mun Sik Choi, Su Chul Han, Jong Hyun Back
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Patent number: 11942156Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.Type: GrantFiled: February 15, 2022Date of Patent: March 26, 2024Assignee: SK hynix Inc.Inventors: Hyeok Jun Choi, Hee Sik Park, Seung Geun Jeong
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Publication number: 20240099114Abstract: A display device may include a first electrode, a second electrode, an emission layer, an intervening layer, and a first encapsulation layer. The second electrode may overlap the first electrode. The emission layer may be disposed between the first electrode and the second electrode, may overlap the first electrode, and may include a light emitting material. The intervening layer may directly contact the second electrode, may be spaced from each of the first electrode and the emission layer, and may include a fluorine compound. A first section of the first encapsulation layer may overlap the emission layer. The intervening layer may be positioned between the second electrode and a second section of the first encapsulation layer.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: Jae Sik KIM, Jae Ik KIM, Jung Sun PARK, Seung Yong SONG, Duck Jung LEE, Yeon Hwa LEE, Joon Gu LEE, Kyu Hwan HWANG
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Publication number: 20240086603Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: In HUH, Jeong-hoon KO, Hyo-jin CHOI, Seung-ju KIM, Chang-wook JEONG, Joon-wan CHAI, Kwang-II PARK, Youn-sik PARK, Hyun-sun PARK, Young-min OH, Jun-haeng LEE, Tae-ho LEE
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Patent number: 11912245Abstract: A device for distributing washer fluid, which includes a case including one or more discharge holes, a rail part located in the case, a pipe assembly moved along the rail part and configured to discharge a washer fluid to the one or more discharge holes, a motor assembly configured to apply a driving force to allow the pipe assembly to be moved along the rail part, a hose engaged with the pipe assembly and integrally moved with the pipe assembly along the rail part, and a controller configured to control the driving force of the motor assembly in response to a cleaning request such that the pipe assembly discharges the washer fluid to a selected discharge hole.Type: GrantFiled: November 10, 2020Date of Patent: February 27, 2024Assignees: Hyundai Motor Company, Kia Motors Corporation, DY Auto CorporationInventors: Jong Min Park, Nak Kyoung Kong, Seung Sik Han, Ki Hong Lee, Jong Wook Lee
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Patent number: 11915790Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.Type: GrantFiled: May 26, 2022Date of Patent: February 27, 2024Assignee: SK hynix Inc.Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
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Patent number: 10686051Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.Type: GrantFiled: August 21, 2018Date of Patent: June 16, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
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Patent number: 10217836Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.Type: GrantFiled: August 25, 2017Date of Patent: February 26, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
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Publication number: 20180358451Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jeong Hwan PARK, Seung Sik PARK, Ha Yong YANG
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Patent number: 10103221Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: GrantFiled: May 18, 2017Date of Patent: October 16, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
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Publication number: 20180261680Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.Type: ApplicationFiled: August 25, 2017Publication date: September 13, 2018Applicant: Magnachip Semiconductor, Ltd.Inventors: Jeong Hwan PARK, Seung Sik PARK, Ha Yong YANG
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Publication number: 20170256607Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: In Su KIM, Jeong Hwan PARK, Seung Sik PARK, Ha Yong YANG
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Patent number: 9691844Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: GrantFiled: November 12, 2015Date of Patent: June 27, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
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Publication number: 20160336393Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: ApplicationFiled: November 12, 2015Publication date: November 17, 2016Applicant: Magnachip Semiconductor, Ltd.Inventors: In Su KIM, Jeong Hwan PARK, Seung Sik PARK, Ha Yong YANG
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Publication number: 20100255252Abstract: Provided is a nano structure composite and a method of manufacturing the same. More specifically, a nano structure composite that includes a substrate, a first layer formed of carbon nano structures on the substrate, and a second layer formed of metal oxide nano structures on the first layer, and a method of manufacturing the same are provided. When the nano structure composite according to the present invention is used, a device having a field emission characteristic higher efficiency than a conventional device can be realized, and also, the device can be manufactured at a lower temperature and at a lower pressure. Thus, manufacturing cost can be reduced and a large scale process can be performed.Type: ApplicationFiled: September 3, 2008Publication date: October 7, 2010Inventors: Sang-Hyeob Kim, Seung-Sik Park, Sang-Woo Kim, Gong-Gu Lee, Sung-Jin Kim, Sunglyul Maeng, Sunyoung Lee, Hey-Jin Myoung