Patents by Inventor Seung-Taek Lim

Seung-Taek Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313498
    Abstract: A display device includes a first substrate, a wire pad in a pad area, first banks in a display area, electrodes on the first banks, a pad electrode base layer on the wire pad, having a greater width than the wire pad, and covering sides of the wire pad, a first insulating layer covering parts of the electrodes and part of the pad electrode base layer, light-emitting elements on the first insulating layer in the display area, respective ends of the light-emitting elements being on different electrodes, contact electrodes on the electrodes and contacting first ends of the light-emitting elements, and a pad electrode upper layer on the first insulating layer in the pad area and directly contacting the pad electrode base layer, wherein the pad electrode base layer includes the same material as the electrodes, and the pad electrode upper layer includes the same material as the contact electrodes.
    Type: Application
    Filed: October 23, 2020
    Publication date: October 7, 2021
    Inventors: Jin Taek KIM, Seung Min LEE, Jung Hwan YI, Hee Keun LEE, Bek Hyun LIM, Kyung Tae CHAE
  • Patent number: 11133015
    Abstract: A method of predicting a channel parameter of an original signal from a downmix signal is disclosed. The method may include generating an input feature map to be used to predict a channel parameter of the original signal based on a downmix signal of an original signal, determining an output feature map including a predicted parameter to be used to predict the channel parameter by applying the input feature map to a neural network, generating a label map including information associated with the channel parameter of the original signal, and predicting the channel parameter of the original signal by comparing the output feature map and the label map.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 28, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Kwon Beack, Woo-taek Lim, Jongmo Sung, Mi Suk Lee, Tae Jin Lee, Hui Yong Kim
  • Publication number: 20210296537
    Abstract: A display device includes: a substrate having a display area and a non-display area; and a pixel in each of a pixel area in the display area. Each of the pixels includes: an insulating layer on the substrate and having an opening; first and second electrodes on the insulating layer and spaced apart from each other; a plurality of light emitting elements in the opening; a first contact electrode electrically connecting one end of the light emitting elements and the first electrode to each other; a second contact electrode electrically connecting another end of the light emitting elements and the second electrode to each other; a first insulating pattern on the first contact electrode; and a second insulating pattern on the second contact electrode. The first insulating pattern and the second insulating pattern are on the same layer and spaced apart from each other.
    Type: Application
    Filed: November 13, 2020
    Publication date: September 23, 2021
    Inventors: Seung Min Lee, Jin Taek Kim, Baek Hyeon Lim, Jin Yeong Kim, Kyung Tae Chae, Jung Hwan Yi, Hee Keun Lee
  • Publication number: 20210281260
    Abstract: Provided is an RF switch device (100) in which body contact regions (190) are formed at respective positions adjacent to or partially overlapping opposite ends of a gate region (110) so that holes in a body of the device can escape or flow in either or both of two directions, rather than in only a single direction.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 9, 2021
    Inventors: Ja-Geon KOO, Jin-Hyo JUNG, Hae-Taek KIM, Seung-Hyun EOM, Ki-Won LIM, Hyun-Joong LEE, Sang-Yong LEE
  • Patent number: 11018501
    Abstract: A directional overcurrent relay using a superconducting fault current limiter voltage as a relay element includes: a current measuring circuit measuring a current of a line connected from a system power source to a load, a voltage measuring circuit measuring a voltage at both ends of a superconducting fault current limiter connected to the line, and a correcting circuit correcting a tripping time Ttrip by using a fault current If that is the current of the line and a superconducting fault current limiter voltage VSFCL that is the voltage at both ends of the superconducting fault current limiter and the tripping time Ttrip is maintained consistently regardless of whether the superconducting fault current limiter operates or not.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: May 25, 2021
    Assignee: Foundation of Soongsil University-Industry Cooperation
    Inventors: Sung Hun Lim, Seung Taek Lim
  • Patent number: 10844853
    Abstract: The present invention relates to a suction pulsation reducing device of a swash plate type compressor, and more particularly, to a suction pulsation reduction apparatus provided on a suction channel formed in a rear head of a swash plate type compressor, in which a moving range of a core portion is limited and all parts to be mounted on a suction channel are integrally formed in a case.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 24, 2020
    Assignee: Hanon Systems
    Inventors: Young Seop Yoon, Seung Taek Lim
  • Publication number: 20200014198
    Abstract: Provided is a directional overcurrent relay using a superconducting fault current limiter voltage as a relay element, and a method for correcting the same. The directional overcurrent relay using a superconducting fault current limiter voltage as a relay element includes: a current measuring circuit measuring a current of a line connected from a system power source to a load, a voltage measuring circuit measuring a voltage at both ends of a superconducting fault current limiter connected to the line, and a correcting circuit correcting a tripping time Ttrip by using a fault current If that is the current of the line and a superconducting fault current limiter voltage VSFCL that is the voltage at both ends of the superconducting fault current limiter and the tripping time Ttrip is maintained consistently regardless of whether the superconducting fault current limiter operates or not.
    Type: Application
    Filed: November 23, 2018
    Publication date: January 9, 2020
    Inventors: Sung Hun Lim, Seung Taek Lim
  • Patent number: 10316831
    Abstract: Disclosed herein is a valve assembly for a variable swash plate compressor. Since an opening hole of a suction reed is enlarged toward a suction port of a valve plate and refrigerant is also introduced into a cylinder bore through the opening hole when the suction port is opened, performance of a compressor may be enhanced by an increase in flow rate.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 11, 2019
    Assignee: HANON SYSTEMS
    Inventors: Sang Woo Bae, Eun Gi Son, Je Su Yun, Se Young Song, Young Seop Yoon, Sung Myung Lee, Hew Nam Ahn, Seung Taek Lim
  • Publication number: 20190170131
    Abstract: The present invention relates to a suction pulsation reducing device of a swash plate type compressor, and more particularly, to a suction pulsation reduction apparatus provided on a suction channel formed in a rear head of a swash plate type compressor, in which a moving range of a core portion is limited and all parts to be mounted on a suction channel are integrally formed in a case.
    Type: Application
    Filed: June 27, 2017
    Publication date: June 6, 2019
    Inventors: Young Seop Yoon, Seung Taek Lim
  • Publication number: 20150086400
    Abstract: Disclosed herein is a valve assembly for a variable swash plate compressor. Since an opening hole of a suction reed is enlarged toward a suction port of a valve plate and refrigerant is also introduced into a cylinder bore through the opening hole when the suction port is opened, performance of a compressor may be enhanced by an increase in flow rate.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Inventors: Sang Woo Bae, Eun Gi Son, Je Su Yun, Se Young Song, Young Seop Yoon, Sung Myung Lee, Hew Nam Ahn, Seung Taek Lim
  • Patent number: 7883942
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-Gee Baek, Kwon-Young Choi, Young-Joon Rhee, Bong-Joo Kang, Seung-Taek Lim, Hyang-Shik Kong, Won-Joo Kim
  • Patent number: 7709304
    Abstract: A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Yong Park, Won-Hee Lee, Il-Gon Kim, Seung-Taek Lim, You-Lee Song, Sahng-Ik Jun
  • Publication number: 20100096176
    Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 22, 2010
    Inventors: Seung-Taek LIM, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
  • Patent number: 7659625
    Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Taek Lim, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
  • Publication number: 20090096105
    Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.
    Type: Application
    Filed: December 12, 2008
    Publication date: April 16, 2009
    Inventors: Seung-Taek LIM, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
  • Publication number: 20080090404
    Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.
    Type: Application
    Filed: November 29, 2007
    Publication date: April 17, 2008
    Inventors: Seung-Taek Lim, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-kyu Song
  • Publication number: 20080044996
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a—Si layer, an extrinsic a—Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a—Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a—Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 21, 2008
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Bum-Gee BAEK, Kwon-Young CHOI, Young-Joon RHEE, Bong-Joo KANG, Seung-Taek LIM, Hyang-Shik KONG, Won-Joo KIM
  • Patent number: 7303987
    Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Taek Lim, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
  • Patent number: 7294855
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-Gee Baek, Kwon-Young Choi, Young-Joon Rhee, Bong-Joo Kang, Seung-Taek Lim, Hyang-Shik Kong, Won-Joo Kim
  • Patent number: D710905
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 12, 2014
    Assignee: Halla Visteon Climate Control Corp.
    Inventors: Bok Ki Park, Eun Gi Son, Seung Taek Lim