Patents by Inventor Seunghun Hong
Seunghun Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8558303Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.Type: GrantFiled: September 23, 2011Date of Patent: October 15, 2013Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Seunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Patent number: 8350602Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.Type: GrantFiled: April 18, 2011Date of Patent: January 8, 2013Assignee: Seoul National University Research & Development Business FoundationInventors: Seunghun Hong, Sung Myung, Kwang Heo
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Patent number: 8343366Abstract: Nanoscale graphene structure fabrication techniques are provided. An oxide nanowire useful as a mask is formed on a graphene layer and then ion beam etching is performed. A nanoscale graphene structure is fabricated by removing a remaining oxide nanowire after the ion beam etching.Type: GrantFiled: September 15, 2008Date of Patent: January 1, 2013Assignee: SNU R&DB FoundationInventors: Seunghun Hong, Joohyung Lee, Tae Hyun Kim
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Publication number: 20120295029Abstract: The invention provides a nanolithographic method, comprising: (i) providing a substrate; (ii) providing a nanoscopic tip coated with a patterning compound; (iii) contacting the coated tip with the substrate so that the patterning compound is applied to the substrate to produce a desired pattern; and (iv) wherein the patterning compound is anchored to the substrate.Type: ApplicationFiled: April 18, 2012Publication date: November 22, 2012Inventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
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Patent number: 8247032Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). The method include the following steps: (i) providing a substrate and a scanning probe microscope tip; (ii) coating the tip with a patterning compound and a solvent to form a wet tip; and (iii) contacting the coated tip with the substrate so that the compound is applied to the substrate so as to produce a desired pattern. The invention also provides substrates patterned by DPN and kits for performing DPN.Type: GrantFiled: October 31, 2007Date of Patent: August 21, 2012Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
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Patent number: 8227179Abstract: Techniques for manufacturing cross-structures of nanostructures, such as nanowires and carbon nanotubes are provided. In one embodiment, a method for manufacturing cross-structures of nanostructures include providing a substrate, patterning a first mask layer on the substrate, adsorbing first nanostructures onto surface regions of the substrate where the first mask layer does not exist, removing the first mask layer from the substrate, patterning a second mask layer on the substrate to which the first nanostructures are adsorbed, and adsorbing second nanostructures onto the surface regions of the substrate where the second mask layer does not exist, under conditions effective to manufacture cross-structures of nanostructures on the substrate.Type: GrantFiled: September 25, 2008Date of Patent: July 24, 2012Assignee: SNU R&DB FoundationInventors: Seunghun Hong, Sung Young Park, Seon Namgung
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Patent number: 8187673Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN, including submicrometer combinatorial arrays, and kits, devices and software for performing DPN. The invention further provides a method of performing AFM imaging in air.Type: GrantFiled: October 31, 2007Date of Patent: May 29, 2012Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
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Patent number: 8163345Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN and kits for performing DPN. The invention further provides a method of performing AFM imaging in air. The method comprises coating an AFM tip with a hydrophobic compound, the hydrophobic compound being selected so that AFM imaging performed using the coated AFM tip is improved compared to AFM imaging performed using an uncoated AFM tip. Finally, the invention provides AFM tips coated with the hydrophobic compounds.Type: GrantFiled: July 31, 2009Date of Patent: April 24, 2012Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
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Publication number: 20120012817Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Seunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Patent number: 8063430Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.Type: GrantFiled: October 20, 2008Date of Patent: November 22, 2011Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Seunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Publication number: 20110210765Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.Type: ApplicationFiled: April 18, 2011Publication date: September 1, 2011Applicant: SEOUL NATIONAL UNIVERSITY RESEARCH & DEVELOPMENT BUSINESS FOUNDATIONInventors: Seunghun Hong, Sung Myung, Kwang Heo
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Patent number: 7968935Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.Type: GrantFiled: August 25, 2008Date of Patent: June 28, 2011Assignee: Seoul National University Research & Development Business FoundationInventors: Seunghun Hong, Sung Myung, Kwang Heo
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Publication number: 20100330345Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN, including submicrometer combinatorial arrays, and kits, devices and software for performing DPN. The invention further provides a method of performing AFM imaging in air.Type: ApplicationFiled: October 31, 2007Publication date: December 30, 2010Inventors: Chad A MIRKIN, Richard Piner, Seunghun Hong
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Patent number: 7744963Abstract: In one aspect, a method of nanolithography is provided, the method comprising providing a substrate; providing a scanning probe microscope tip; coating the tip with a deposition compound; and subjecting said coated tip to a driving force to deliver said deposition compound to said substrate so as to produce a desired pattern. Another aspect of the invention provides a tip for use in nanolithography having an internal cavity and an aperture restricting movement of a deposition compound from the tip to the substrate. The rate and extent of movement of the deposition compound through the aperture is controlled by a driving force.Type: GrantFiled: October 31, 2007Date of Patent: June 29, 2010Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Seunghun Hong, Vinayak P. Dravid
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Patent number: 7722928Abstract: In one aspect, a method of nanolithography is provided using a driving force to control the movement of a deposition compound from a scanning probe microscope tip to a substrate. Another aspect of the invention provides a tip for use in nanolithography having an internal cavity and an aperture restricting movement of a deposition compound from the tip to the substrate. The rate and extent of movement of the deposition compound through the aperture is controlled by a driving force.Type: GrantFiled: April 7, 2005Date of Patent: May 25, 2010Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Seunghun Hong, Vinayak P. Dravid
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Publication number: 20100098857Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN and kits for performing DPN. The invention further provides a method of performing AFM imaging in air. The method comprises coating an AFM tip with a hydrophobic compound, the hydrophobic compound being selected so that AFM imaging performed using the coated AFM tip is improved compared to AFM imaging performed using an uncoated AFM tip.Type: ApplicationFiled: July 31, 2009Publication date: April 22, 2010Inventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
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Publication number: 20100044777Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.Type: ApplicationFiled: August 25, 2008Publication date: February 25, 2010Applicant: SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATIONInventors: Seunghun Hong, Sung Myung, Kwang Heo
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Publication number: 20100047444Abstract: Techniques for assembling nanostructures on a substrate are provided. Methods for assembling nanostructures on a substrate may involve, but are not limited to, detaching nanostructures from a wafer, passing the nanostructures through a filter, and assembling the nanostructures onto a patterned substrate.Type: ApplicationFiled: August 25, 2008Publication date: February 25, 2010Inventors: Seunghun Hong, Byeongju Kim
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Publication number: 20100047581Abstract: Techniques for assembling actin filaments on a substrate and nanodevices including actin filaments are provided.Type: ApplicationFiled: August 25, 2008Publication date: February 25, 2010Inventors: Seunghun Hong, Kyung-Eun Byun
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Publication number: 20100045610Abstract: A transparent conductive film comprised of a carbon nanotube network and indium tin oxide composite and a method for manufacturing the transparent conductive film are provided.Type: ApplicationFiled: August 20, 2008Publication date: February 25, 2010Applicant: SNU R&DB FOUNDATIONInventors: Seunghun Hong, Moon Gyu Sung