Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.

Abstract: A display device may include a first electrode, a second electrode, an emission layer, an intervening layer, and a first encapsulation layer. The second electrode may overlap the first electrode. The emission layer may be disposed between the first electrode and the second electrode, may overlap the first electrode, and may include a light emitting material. The intervening layer may directly contact the second electrode, may be spaced from each of the first electrode and the emission layer, and may include a fluorine compound. A first section of the first encapsulation layer may overlap the emission layer. The intervening layer may be positioned between the second electrode and a second section of the first encapsulation layer.

Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.

Abstract: A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal.

Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.

Abstract: The present invention relates to a composition for preventing or treating chronic allograft dysfunction, comprising bisphosphonate which is used as a therapeutic agent for osteoporosis. The composition for preventing or treating chronic allograft dysfunction, comprising bisphosphonate, according to the present invention has an excellent prophylactic and/or therapeutic effect on chronic allograft dysfunction caused by a gradual decrease in the function of a transplanted tissue or organ which occurs after tissue or organ transplantation surgery, and thus is expected to be able to remarkably increase a long-term survival after transplantation surgery.

Abstract: A neural network engine configured to perform neural network computations. The neural network engine includes a first memory block configured to provide a first operand; a second memory block configured to provide a second operand; a synapse array configured to produce partial products of the first and second operands, wherein the synapse array is located outside of the first and second memory blocks; and, an accumulator array to perform summation of the partial products produced by the synapse array.

Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal.

Abstract: A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.

Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.

Abstract: A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.

Abstract: A display device for a vehicle includes a main body, a guide, and a flexible display. The flexible display is configured to be inserted between a pair of guide plates of the guide. The pair of guide plates are transparent, and an area of the flexible display positioned between the pair of guide plates is configured to vary. The display device allows a front area of the vehicle to be viewed through the transparent guide plates, and allows a rear area of the vehicle to be disposed on the flexible display. The flexible display is configured to be protected by the pair of guide plates and deformed along the pair of guide plates.

Abstract: A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.

Abstract: A neural network unit is disclosed.

Abstract: A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

Abstract: A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

Abstract: An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A display device for a vehicle includes a main body, a guide, and a flexible display. The flexible display is configured to be inserted between a pair of guide plates of the guide. The pair of guide plates are transparent, and an area of the flexible display positioned between the pair of guide plates is configured to vary. The display device allows a front area of the vehicle to be viewed through the transparent guide plates, and allows a rear area of the vehicle to be disposed on the flexible display. The flexible display is configured to be protected by the pair of guide plates and deformed along the pair of guide plates.