Patents by Inventor SEUNGKEE MIN

SEUNGKEE MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018629
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, Inc.
    Inventors: Seungkee Min, Margaret A. Szymanowski
  • Publication number: 20200403576
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventors: Seungkee Min, Margaret A. Szymanowski
  • Patent number: 10069462
    Abstract: A multiple-stage RF amplifier and a packaged amplifier device include driver and final-stage transistors, each having a control terminal, a first current-carrying terminal, and a second current-carrying terminal. The control terminal of the final-stage transistor is electrically coupled to the first current-carrying terminal of the driver transistor. The amplifier further includes an inter-stage circuit coupled between the first current carrying terminal of the driver transistor and a voltage reference node. The inter-stage circuit includes a first inductance, a first capacitor, and a second capacitor. The first inductance and the first capacitor are coupled in series between the first current carrying terminal and the voltage reference node, with an intermediate node between the first inductance and the first capacitor. The second capacitor has a first terminal electrically coupled to the intermediate node and a second terminal electrically coupled to the voltage reference node.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 4, 2018
    Assignee: NXP USA, INC.
    Inventors: Seungkee Min, Margaret A. Szymanowski, Henry Andre Christange
  • Publication number: 20180248521
    Abstract: A multiple-stage RF amplifier and a packaged amplifier device include driver and final-stage transistors, each having a control terminal, a first current-carrying terminal, and a second current-carrying terminal. The control terminal of the final-stage transistor is electrically coupled to the first current-carrying terminal of the driver transistor. The amplifier further includes an inter-stage circuit coupled between the first current carrying terminal of the driver transistor and a voltage reference node. The inter-stage circuit includes a first inductance, a first capacitor, and a second capacitor. The first inductance and the first capacitor are coupled in series between the first current carrying terminal and the voltage reference node, with an intermediate node between the first inductance and the first capacitor. The second capacitor has a first terminal electrically coupled to the intermediate node and a second terminal electrically coupled to the voltage reference node.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Inventors: Seungkee Min, Margaret A. Szymanowski, Henry Andre Christange
  • Patent number: 9331642
    Abstract: Embodiments of an integrated resistor may be incorporated into monolithic transistor circuits and packaged RF amplifier devices. An embodiment of an integrated resistor includes a semiconductor substrate and a resistor formed over the top surface of the semiconductor substrate from resistive material. The resistor includes at least first and second resistive sections. The first resistive section is tapered so that the first resistive section widens toward an input end of the resistor. The second resistive section is coupled in series with the first resistive section. According to a further embodiment, the second resistive section also is tapered so that the second resistive section widens toward an output end of the resistor. According to another further embodiment, a third resistive section with one or more meanders is coupled in series between the first and second resistive sections.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sarmad K. Musa, Seungkee Min, Margaret A. Szymanowski
  • Publication number: 20150381122
    Abstract: Embodiments of an integrated resistor may be incorporated into monolithic transistor circuits and packaged RF amplifier devices. An embodiment of an integrated resistor includes a semiconductor substrate and a resistor formed over the top surface of the semiconductor substrate from resistive material. The resistor includes at least first and second resistive sections. The first resistive section is tapered so that the first resistive section widens toward an input end of the resistor. The second resistive section is coupled in series with the first resistive section. According to a further embodiment, the second resistive section also is tapered so that the second resistive section widens toward an output end of the resistor. According to another further embodiment, a third resistive section with one or more meanders is coupled in series between the first and second resistive sections.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: SARMAD K. MUSA, SEUNGKEE MIN, MARGARET A. SZYMANOWSKI