Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract: Techniques for removing crosstalk from a system, e.g., an audio system, having first and second (e.g., left and right) channels. In an aspect, first and second output voltages of corresponding first and second amplifiers are sampled during a calibration mode, in which one of the amplifiers is driven with a reference voltage, and the output of the other of the amplifiers is configured to have a high impedance. The sampled first and second output voltages may be digitized for processing by a processor to estimate a crosstalk removal function. The crosstalk removal function may then be multiplied with the input signals and added in a cross-channel manner to the first and second input signals prior to amplification to remove crosstalk from the system. In certain aspects, multiple reference voltages may be applied during the calibration mode to improve the estimate of the crosstalk removal function.

Abstract: Techniques for removing crosstalk from a system, e.g., an audio system, having first and second (e.g., left and right) channels. In an aspect, first and second output voltages of corresponding first and second amplifiers are sampled during a calibration mode, in which one of the amplifiers is driven with a reference voltage, and the output of the other of the amplifiers is configured to have a high impedance. The sampled first and second output voltages may be digitized for processing by a processor to estimate a crosstalk removal function. The crosstalk removal function may then be multiplied with the input signals and added in a cross-channel manner to the first and second input signals prior to amplification to remove crosstalk from the system. In certain aspects, multiple reference voltages may be applied during the calibration mode to improve the estimate of the crosstalk removal function.

Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract: A linear sampling circuit is constructed with an p-channel and an n-channel field effect transistor (FET). A source node of the p-channel FET is coupled to a drain node of the n-channel FET and a drain node of the p-channel FET is coupled to a source node of the n-channel FET. A sampling clock is coupled to the gate node of each FET. A first side of the linear sampling circuit is connected to an analog or RF signal source and a far side of the linear sampling circuit is connected to a holding capacitor. The a n-channel FET has a n-channel width. A p-channel FET has a p-channel width. The p-channel width is larger than the n-channel width in order to increase the linearity of the on-resistance of the resulting switch.

Abstract: A linear switch is incorporated into an active sample and hold switch. The active sample and hold circuit is symmetric and configured to accept a balanced input. Two linear switches couple a positive input signal of the balanced input to two different sampling capacitors. After the sampling capacitors are charged, another set of switches configures the sampling capacitors such that one of the sampling capacitor is in the feed back of an op amp and the other is connected from the input of the op amp to ground. In this configuration, the circuit has a gain of two and the output of the op amp is twice the voltage sampled by the sampling capacitors.

Abstract: A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The .SIGMA..DELTA. ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic range performance. The loops can be enabled or disabled based on the required dynamic range and a set of dynamic range thresholds. The .SIGMA..DELTA. ADC is also designed with adjustable bias current. The dynamic range of the .SIGMA..DELTA. ADC varies approximately proportional to the bias current. By adjusting the bias current, the required dynamic range can be provided by the .SIGMA..DELTA. ADC with minimal power consumption. A reference voltage of the .SIGMA..DELTA. ADC can be descreased when high dynamic range is not required, thereby allowing for less bias current in the .SIGMA..DELTA. ADC and supporting circuitry. The dynamic range of the .SIGMA..DELTA. ADC is a also function of the oversampling ratio which is proportional to the sampling frequency.

Abstract: A receiver comprising a sigma-delta analog-to-digital converter (.SIGMA..DELTA. ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling .SIGMA..DELTA. receivers, the sampling frequency is less than twice the center frequency of the input signal into the .SIGMA..DELTA. ADC. For Nyquist sampling .SIGMA..DELTA. receivers, the sampling frequency is at least twice the highest frequency of the input signal into the .SIGMA..DELTA. ADC. For baseband .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is approximately zero or DC. For bandpass .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is greater than zero.

Abstract: A bandpass .SIGMA..DELTA. DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a .SIGMA..DELTA. ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 .SIGMA..DELTA. ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass .SIGMA..DELTA.