Abstract: Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a vector register for transmission to common memory or as operands to a functional unit, the vector register immediately becomes available to receive and store elements of a vector from common memory or a functional unit. The element-by-element storing takes place simultaneously with the element-by-element reading, and trails the reading by at least one element so as to not overwrite elements yet to be read. Through the use of this technique a vector register can be loaded with a vector for a subsequent operation without having to wait for the completion of the previous operation which uses the same vector register.

Abstract: A method and apparatus for interconnecting electronic circuits using nearly pure soft annealed gold mechanically compressed within through-plated holes. The invention has its application in attaching integrated circuit dice directly to circuit boards by ball bonding gold wires to the bonding pads of the integrated circuit dice in a substantially perpendicular relationship to the surfaces of the dice and inserting the gold leads into through-plated holes of circuit boards which provide an electrical and a mechanical connection once the leads are compressed within the through-plated holes. The present invention also finds its application in the interconnection of sandwiched circuit board assemblies where soft gold lead wires are inserted into axially aligned through-plated holes of the circuit boards and compressed so that the gold lead wires compress and buckle within the through-plated holes, forming an electrical connection between the circuit boards.

Abstract: A method and apparatus for interconnecting electronic circuit boards through the use of twisted wire jumpers which are formed from multifilament wire and which have enlarged bird cages formed along the pins. The pins are drawn through a stack of circuit boards to position the cages in contact with interconnection apertures located in the printed circuit boards. The frictional engagement of the cages in the apertures provides both electrical inter connection of, and mechanical coupling between the printed circuit boards.

Abstract: A cooling system employs a cooling liquid and a cooling gas in a combined thermodynamic cycle to overcome the flow resistance of dense assemblies of heat generating components and to improve heat transfer by inducing turbulence, thereby reducing the effects of thermal hysteresis and boundary layer formation. Sensible heat gain to the cooling liquid and gas and latent heat of vaporization of the cooling liquid also occur in channels through and over the components. The flow of cooling gas propels the cooling liquid through the channels. The cooling system is advantageous for cooling electronic components such as integrated circuits which exhibit relatively high degree of energy and physical density, in supercomputers. The cooling system may also be advantageously combined with an immersion cooling system for the power supply components in the computer.

Abstract: A method and apparatus for interconnecting electronic circuit boards through the use of twisted wire jumpers which are formed from multifilament wire and which have enlarged bird cages formed along the pins. The pins are drawn through a stack of circuit boards to position the cages in contact with interconnection aperture located in the printed circuit boards. The frictional engagement of the cages in the apertures provides both electrical interconnection of, and mechanical coupling between the printed circuit boards.This application is a division of co pending patent application Her. No. 07/347,507, filed May 4, 1989, now U.S. Pat. No. 5,014,419, issued May 14, 1991, U.S. Pat. application Ser. No. 07/347,507 was a continuation-in-part of application Ser. No. 07/053,142, filed May 21, 1989, now U.S. Pat. No. 5,054,192, issued Oct. 8, 1991. All of these applications and patents are assigned to the same assignee.

Abstract: A method and apparatus for interconnecting electronic circuits using nearly pure soft annealed gold mechanically compressed within through-plated holes. The invention has its application in attaching integrated circuit dice directly to circuit boards by ball bonding gold wires to the bonding pads of the integrated circuit dice in a substantially perpendicular relationship to the surfaces of the dice and inserting the gold leads into through-plated holes of circuit boards which provide an electrical and a mechanical connection once the leads are compressed within the through-plated holes. The present invention also finds its application in the interconnection of sandwiched circuit board assemblies where soft gold lead wires are inserted into axially aligned through-plated holes of the circuit boards and compressed so that the hold lead wires compress and buckle within the through-plated holes, forming an electrical connection between the circuit boards.

Abstract: A method and apparatus for interconnecting electronic circuits using nearly pure soft annealed gold mechanically compressed within through-plated holes. The invention has its application in attaching integrated circuit dice directly to circuit boards by ball bonding gold wires to the bonding pads of the integrated circuit dice in a substantially perpendicular relationship to the surfaces of the disc and inserting the gold leads into through-plated holes of circuit boards which provide an electrical and a mechanical connection once the leads are compressed within the through-plated holes. The present invention also finds its application in the interconnection of sandwiched circuit board assemblies where soft gold lead wires are inserted into axially aligned through-plated holes of the circuit boards and compressed so that the gold lead wires compress and buckle within the through-plated holes, forming an electrical connection between the circuit boards.

Abstract: A method and apparatus for interconnecting electronic circuit boards through the use of twisted wire jumpers which are formed from multifilament wire and which have enlarged bird cages formed along the pins. The pins are drawn through a stack of circuit boards to position the cages in contact with interconnection apertures located in the printed circuit boards. The frictional engagement of the cages in the apertures provides both electrical inter connection of, and mechanical coupling between the printed circuit boards.

Abstract: A gallium arsenide logic design system is described for designing custom or semi-custom LSI integrated circuits using standard cells from a cell library. D-MESFET transistors and Schottky diodes are used for implementing the cell types in gallium arsenide to produce performance levels of less than 150 pico-second per gate propagation delay. Each integrated circuit die is built from a cell library containing three standard cells. The limitation on the number of standard cells used for logic design allows for fast and efficient turnaround time between logic design and fabrication. A minumum number of masks are required for implementing the custom integrated circuit due to the efficient design of the cell types. The placement and interconnect of the cells on the die are also performed in an efficient manner due to the predefined allowable locations for cell placement and the predefined allowable route channels for the interconnect.

Abstract: A logic system preferably for gallium arsenide integrated circuits uses dynamic pulsed logic gates which switch on each clock pulse, with the logical state of an output or data line being indicated by the phase of the pulsed output, which may be shifted or modulated with respect to a reference. An individual logic gate has a first signal generator having a capacitor which is either charged up or discharged during a set-up phase of a clock cycle, depending upon applied input logic signals. During a second, transmit phase of the clock signal, the signal developed on the capacitor is output from the gate. A second signal generator is an inverting slave of the first, and outputs the inverse logic state during the succeeding set-up phase of the first generator. With each gate switching on every clock period, all switching noise appearing in the ground or power supplies is at or above the clock frequency and can simply be filtered out with small chip capacitors, providing improvement in noise immunity.

Abstract: An immersion cooling system for high density electronic assemblies such as computers includes a container holding an inert cooling liquid, and stacks of circuit modules arranged in a generally radial pattern within the container. Coolant supply columns and coolant removal columns alternate between adjacent stacks around the pattern. The coolant supply columns include distribution manifolds which distribute incoming coolant at all levels to provide a flow of coolant to all circuit modules. The flow passes between adjacent boards of the modules and preferably along flow channels formed by the circuit chips aligned in rows. After passing across the circuit modules the heated coolant rises in coolant removal columns and flows over standpipes for removal from the container, and a pump and heat exchanger recools and recirculates the coolant. Pump up and pump down systems are also provided for withdrawing the coolant to a reservoir for servicing the circuitry.

Abstract: Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate.