Patents by Inventor Shahab OVEIS GHARAN
Shahab OVEIS GHARAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240048270Abstract: An optical transmitter device includes a digital signal processor (DSP) having digital hardware. The DSP is operative to generate shaped bits from a first set of information bits, and to apply a systematic forward error correction (FEC) scheme to encode the shaped bits and a second set of information bits, where the first set of information bits and the second set of information bits are disjoint sets. Unshaped bits and the shaped bits are mapped to selected symbols or are used to select symbols from one or more constellations. The selected symbols are mapped to physical dimensions. Each unshaped bit is either one of the second set of information bits or one of multiple parity bits resulting from the FEC encoding. In this manner, a target spectral efficiency is achieved.Type: ApplicationFiled: October 11, 2023Publication date: February 8, 2024Inventors: Hamid EBRAHIMZAD, Michael REIMER, Vladimir S. GRIGORYAN, Shahab OVEIS GHARAN
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Patent number: 11876525Abstract: An apparatus comprises circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC), circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal, and circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.Type: GrantFiled: May 10, 2022Date of Patent: January 16, 2024Assignee: Ciena CorporationInventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard
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Patent number: 11831431Abstract: An optical transmitter device (14) includes a digital signal processor ‘DSP’ (20) having digital hardware (30). The DSP is operative to generate (102,202,302) shaped bits from a first set of information bits, and to apply (104,204,304) a systematic forward error correction ‘FEC’ scheme to encode the shaped bits and a second set of information bits, where the first set of information bits and the second set of information bits are disjoint sets. Unshaped bits and the shaped bits are mapped to selected symbols or are used to select symbols from one or more constellations. The selected symbols are mapped to physical dimensions. Each unshaped bit is either one of the second set of information bits or one of multiple parity bits resulting from the FEC encoding. In this manner, a target spectral efficiency is achieved.Type: GrantFiled: October 11, 2019Date of Patent: November 28, 2023Assignee: Ciena CorporationInventors: Hamid Ebrahimzad, Michael Reimer, Vladimir S. Grigoryan, Shahab Oveis Gharan
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Publication number: 20230370077Abstract: An apparatus comprises circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC), circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal, and circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Ciena CorporationInventors: Ramin BABAEE, Shahab OVEIS GHARAN, Martin BOUCHARD
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Publication number: 20230370079Abstract: A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2N?1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Ciena CorporationInventors: Ramin BABAEE, Shahab OVEIS GHARAN, Martin BOUCHARD
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Patent number: 11817873Abstract: A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2N?1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.Type: GrantFiled: May 10, 2022Date of Patent: November 14, 2023Assignee: Ciena CorporationInventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard
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Patent number: 11818242Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.Type: GrantFiled: September 10, 2020Date of Patent: November 14, 2023Inventors: Ahmad Abdo, Shahab Oveis Gharan, Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw
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Patent number: 11652566Abstract: In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.Type: GrantFiled: July 30, 2018Date of Patent: May 16, 2023Assignee: CIENA CORPORATIONInventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
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Publication number: 20230017120Abstract: A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Shahab OVEIS GHARAN, Mohammad Ehsan SEIFI, Kim B. ROBERTS
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Publication number: 20220321247Abstract: A system is configured to measure (602) a forward error correction (FEC) decoding property (216) associated with applying FEC decoding (214) to FEC-encoded bits or symbols at a receiver device (202) deployed in a communication network (100). The system is configured to provide (606) an assessment of operating conditions of the receiver device based on the FEC decoding property. The FEC decoding property comprises, for example, a distribution of a number of iterations of a FEC decoding operation applied to a plurality of FEC blocks processed within a period of time. In some examples, the FEC decoding property comprises any one of heat, temperature, current, voltage, active clock cycles, idle clock cycles, activity of parallel engines, activity of pipeline stages, and input or output buffer fill level of the FEC decoding. The assessment is based, for example, on a comparison between the FEC decoding property and reference FEC data (218).Type: ApplicationFiled: September 30, 2020Publication date: October 6, 2022Inventors: Andrew D. SHINER, Shahab OVEIS GHARAN, Michael HUBBARD, Kim B. ROBERTS
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Patent number: 11463105Abstract: A transmitter (200) generates (602) an encoded vector (404) by encoding (406) a data vector (402), the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits (604) a signal representing the encoded vector over a communication channel. A receiver (300) determines (702) a vector estimate (502) from the signal and recovers (716) the data vector from the vector estimate by sequentially decoding (706, 710, 714) the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.Type: GrantFiled: June 30, 2020Date of Patent: October 4, 2022Assignee: CIENA CORPORATIONInventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim Roberts
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Patent number: 11451367Abstract: A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.Type: GrantFiled: September 24, 2021Date of Patent: September 20, 2022Assignee: Ciena CorporationInventors: Shahab Oveis Gharan, James St. Leger Harley, Tung Trong Nguyen
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Patent number: 11451304Abstract: Upon receiving a communications signal conveying symbols at a symbol period T, a receiver applies filter coefficients to a digital representation of the communications signal, thereby generating filtered signals having a shape in the frequency domain characterized by a bandwidth expansion factor ?, where components of the filtered signals correspond to angular frequencies ? = - ? ? ( 1 + ? ) T ? ? … - ? ? ( 1 - ? ) T , + ? ? ( 1 - ? ) T ? ? … + ? ? ( 1 + ? ) T . The receiver calculates first-order components from a first phase derivative of the components at a first differential distance, second-order components from a second phase derivative of the first-order components at a second differential distance, and composite second-order components from an average of the second-order components over multiple time intervals.Type: GrantFiled: November 11, 2021Date of Patent: September 20, 2022Assignee: CIENA CORPORATIONInventors: Tung Trong Nguyen, Timothy James Creasy, Shahab Oveis Gharan
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Publication number: 20220294604Abstract: A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.Type: ApplicationFiled: September 24, 2021Publication date: September 15, 2022Inventors: Shahab OVEIS GHARAN, James St. Leger HARLEY, Tung Trong NGUYEN
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Publication number: 20220158657Abstract: A transmitter (200) generates (602) an encoded vector (404) by encoding (406) a data vector (402), the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits (604) a signal representing the encoded vector over a communication channel. A receiver (300) determines (702) a vector estimate (502) from the signal and recovers (716) the data vector from the vector estimate by sequentially decoding (706, 710, 714) the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.Type: ApplicationFiled: June 30, 2020Publication date: May 19, 2022Inventors: Shahab OVEIS GHARAN, Mohammad Ehsan SEIFI, Kim ROBERTS
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Patent number: 11336367Abstract: A method performed at a transmitter comprises generating a set of digital signals representing a constellation point, each dimension of the point being uniquely represented by m bits, where m?{1, 2, 3}; applying a linear polyphase filter to a digital signal of the set, the linear polyphase filter pre-compensating for a linear transfer function of an electro-optic path of the digital signal and generating a first filtered signal having a roll-off factor ?, where ? is a positive real number satisfying ??1; applying a nonlinear polyphase filter to the digital signal, in parallel to applying the linear polyphase filter to the digital signal, the nonlinear polyphase filter generating a second filtered signal representing nonlinear noise in the electro-optic path; calculating a pre-compensated digital signal from a difference between the first and second filtered signals; and transmitting an optical signal based on the pre-compensated digital signal.Type: GrantFiled: August 30, 2021Date of Patent: May 17, 2022Assignee: IENA CORPORATIONInventors: Shahab Oveis Gharan, James St. Leger Harley, Kendal Zimmer, Christian Bourget
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Publication number: 20220085894Abstract: A transmitter maps an N-bit sequence to a point selected from a four-dimensional (4D) constellation consisting of 2N points which form a subset of a Cartesian product of first and second two-dimensional (2D) constellations, the first constellation consisting of M1 points divided into first, second, and third points, and the second constellation consisting of M2 points divided into fourth, fifth, and sixth points, wherein M1, M2?5, and wherein log2(M1×M2)>N. The subset includes any 4D point that is generated by combining any one of the M1 points and any one of the fourth points; includes any 4D point that is generated by combining any one of the first points and any one of M2 points; and excludes any 4D point that is generated by combining any third point and any sixth point. An optical signal representing the selected point is transmitted to a receiver.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Applicant: Ciena CorporationInventors: Shahab OVEIS GHARAN, Michael Andrew REIMER, James St. Leger HARLEY
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Patent number: 11277206Abstract: A transmitter maps an N-bit sequence to a point selected from a four-dimensional (4D) constellation consisting of 2N points which form a subset of a Cartesian product of first and second two-dimensional (2D) constellations, the first constellation consisting of M1 points divided into first, second, and third points, and the second constellation consisting of M2 points divided into fourth, fifth, and sixth points, wherein M1, M2?5, and wherein log2(M1×M2)>N. The subset includes any 4D point that is generated by combining any one of the M1 points and any one of the fourth points; includes any 4D point that is generated by combining any one of the first points and any one of M2 points; and excludes any 4D point that is generated by combining any third point and any sixth point. An optical signal representing the selected point is transmitted to a receiver.Type: GrantFiled: September 11, 2020Date of Patent: March 15, 2022Assignee: Ciena CorporationInventors: Shahab Oveis Gharan, Michael Andrew Reimer, James St. Leger Harley
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Publication number: 20220069919Abstract: An optical transmitter device (14) includes a digital signal processor ‘DSP’ (20) having digital hardware (30). The DSP is operative to generate (102,202,302) shaped bits from a first set of information bits, and to apply (104,204,304) a systematic forward error correction ‘FEC’ scheme to encode the shaped bits and a second set of information bits, where the first set of information bits and the second set of information bits are disjoint sets. Unshaped bits and the shaped bits are mapped to selected symbols or are used to select symbols from one or more constellations. The selected symbols are mapped to physical dimensions. Each unshaped bit is either one of the second set of information bits or one of multiple parity bits resulting from the FEC encoding. In this manner, a target spectral efficiency is achieved.Type: ApplicationFiled: October 11, 2019Publication date: March 3, 2022Inventors: Hamid EBRAHIMZAD, Michael REIMER, Vladimir S. GRIGORYAN, Shahab OVEIS GHARAN
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Patent number: 11239929Abstract: A receiver is configured to detect, at a communication interface, a received signal that suffers from degradations incurred over a communication channel. The receiver applies an adaptive filter to a series of received blocks of a digital representation of the received signal, thereby generating respective filtered blocks, where each received block represents 2N frequency bins, and where N is a positive integer. The receiver calculates coefficients for use by the adaptive filter on a jth received block as a function of (i) error estimates associated with an (j?D?1)th filtered block, where D is a positive integer representing a number of blocks, and where j is a positive integer greater than (D?1); and (ii) an inverse of an approximate covariance matrix associated with the (j?D?1)th received block, where the approximate covariance matrix is a diagonal matrix of size L×L, and where L is a positive integer lower than 2N.Type: GrantFiled: March 16, 2021Date of Patent: February 1, 2022Assignee: Ciena CorporationInventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard, Kim B. Roberts