Patents by Inventor Shahab Siddiqui

Shahab Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326112
    Abstract: A method of cleaning a low-k spacer cavity by a low energy RF plasma at a specific substrate temperature for a defect free epitaxial growth of Si, SiGe, Ge, III-V and III-N and the resulting device are provided. Embodiments include providing a substrate with a low-k spacer cavity; cleaning the low-k spacer cavity with a low energy RF plasma at a substrate temperature between room temperature to 600° C.; and forming an epitaxy film or a RSD in the low-k spacer cavity subsequent to the low energy RF plasma cleaning.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Shahab SIDDIQUI, Hamed PARVANEH, Mira PARK, Annie LEVESQUE, Yinxiao YANG, Hongyi MI, Asli SIRMAN
  • Publication number: 20190318966
    Abstract: A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10438853
    Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Beth Baumert, Abu Naser M. Zainuddin, Luigi Pantisano
  • Publication number: 20190305105
    Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Qun GAO, Christopher NASSAR, Sugirtha KRISHNAMURTHY, Domingo Antonio FERRER LUPPI, John SPORRE, Shahab SIDDIQUI, Beth BAUMERT, Abu ZAINUDDIN, Jinping LIU, Tae Jeong LEE, Luigi PANTISANO, Heather LAZAR, Hui ZANG
  • Patent number: 10395993
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10361289
    Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
  • Publication number: 20190157157
    Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Beth Baumert, Abu Naser M. Zainuddin, Luigi Pantisano
  • Patent number: 10106892
    Abstract: Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Abu Naser Zainuddin, Beth Baumert, Suresh Uppal
  • Patent number: 9806161
    Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahrukh A. Khan, Unoh Kwon, Shahab Siddiqui, Sean M. Polvino, Joseph F. Shepard, Jr.
  • Patent number: 9789654
    Abstract: A method for manufacturing a silicone hydrogel contact lens is described that comprises curing a polymerizable composition comprising at least one siloxane monomer and at least one hydrophilic vinyl-containing monomer in a contact lens mold comprising a molding surface having a coating comprising a hydrophilic polymer. The hydrophilic coating is not solubilized by the polymerizable composition during the curing step. The resulting polymeric lens body is removed from the mold, washed to remove any of the hydrophilic polymer that may have transferred from the mold surface to the lens during the curing or lens removal process, and packaged to provide a silicone hydrogel contact lens having a contact angle that is lower than what it would otherwise be had the lens been cured in the same contact lens mold lacking the hydrophilic coating.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignee: CooperVision International Holding Company, LP
    Inventors: Ian Bruce, Charlie Chen, Robin Frith, Rachel Marullo, David Morsley, AKM Shahab Siddiqui, Victoria Tran
  • Publication number: 20170294519
    Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Shahrukh A. Khan, Unoh Kwon, Shahab Siddiqui, Sean M. Polvino, Joseph F. Shepard, JR.
  • Patent number: 9741657
    Abstract: A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Shahab Siddiqui, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 9741720
    Abstract: A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Balaji Kannan, Siddarth Krishnan
  • Publication number: 20170170077
    Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui
  • Patent number: 9673108
    Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui
  • Patent number: 9625616
    Abstract: A method is provided for manufacturing ophthalmically-acceptable, distortion-free silicone hydrogel contact lenses without the use of volatile organic solvents in the manufacturing process. The contact lenses are extract with an extraction liquid comprising an aqueous solution of a non-volatile organic solvent, such as ethyl lactate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 18, 2017
    Assignee: CooperVision International Holding Company, LP
    Inventors: Yuwen Liu, AKM Shahab Siddiqui, Yuan Ji, Junhao Ge
  • Publication number: 20170025315
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Application
    Filed: October 4, 2016
    Publication date: January 26, 2017
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 9515164
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 9498924
    Abstract: Ophthalmic lens molds made from one or more thermoplastic polymer having a low level of UV light transmittance (UV % T) ophthalmic lenses including silicone hydrogel contact lenses molded using these thermoplastic polymer having low UV % T, and methods of manufacturing ophthalmic lenses by cast molding a polymerizable composition in mold members formed of these thermoplastic polymers having low UV % T and curing the polymerizable composition using UV light are described.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: November 22, 2016
    Assignee: CooperVision International Holding Company, LP
    Inventors: Lee Darren Norris, Edyta S. Bialek, Sarah L. Almond, David Robert Morsley, A. K. M. Shahab Siddiqui, Richard C. Rogers, Ian Bruce, Benjamin S. Sheader
  • Patent number: 9478425
    Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui