Abstract: An integrated circuit comprises a silicon cylinder having a sidewall upon which a plurality of semiconductor devices have been printed, one or more electrical leads electrically connected to each semiconductor device, and a plurality of radial wiring interconnects projecting outward from the sidewall.

Abstract: A structure including a Si1-xGex substrate and a distributed Bragg reflector layer disposed directly onto the substrate. The distributed Bragg reflector layer includes a repeating pattern that includes at least one aluminum nitride layer and a second layer having the general formula AlyGa1-yN. Another aspect of the present invention is various devices including this structure. Another aspect of the present invention is directed to a method of forming such a structure comprising providing a Si1-xGex substrate and depositing a distributed Bragg reflector layer directly onto the substrate. Another aspect of the present invention is directed to a photodetector or photovoltaic cell device, including a Si1-xGex substrate device, a group III-nitride device and contacts to provide a conductive path for a current generated across at least one of the Si1-xGex substrate device and the group III-nitride device upon incident light.

Abstract: A structure including a Si1-xGex substrate and a distributed Bragg reflector layer disposed directly onto the substrate. The distributed Bragg reflector layer includes a repeating pattern that includes at least one aluminum nitride layer and a second layer having the general formula AlyGa1-yN. Another aspect of the present invention is various devices including this structure. Another aspect of the present invention is directed to a method of forming such a structure comprising providing a Si1-xGex substrate and depositing a distributed Bragg reflector layer directly onto the substrate. Another aspect of the present invention is directed to a photodetector or photovoltaic cell device, including a Si1-xGex substrate device, a group III-nitride device and contacts to provide a conductive path for a current generated across at least one of the Si1-xGex substrate device and the group III-nitride device upon incident light.

Abstract: A photo mask having at least 2 mask pattern layers disposed to collimate light patterns passing through the mask. An improved optical photo lithographic system utilizing light collimating photo masks to improve resolution, depth of focus and field size. A method of manufacturing integrated circuit chips utilizing light collimating photo mask technology.

Abstract: A photomask (8) protected against electrostatic damage and a method of manufacturing such a photomask is disclosed. The photomask (8) comprises a transparent substrate (10) on which is deposited an opaque pattern such as lines (12), (14), (16) and (18). A transparent conductive film (30) is deposited over the substrate (10) and pattern such that the various portions of the pattern (lines (12), (14), (16) and (18)) are all maintained at the same electrical potential thereby preventing damage due to an electrostatic discharge.

Abstract: A photomask (19) protected against electrostatic damage and a method of manufacturing such a photomask is disclosed. The photomask (8) comprises a transparent substrate (10) on which is deposited an opaque pattern such as lines (12), (14), (16) and (18). A transparent conductive film (30) is deposited over the substrate (10) and pattern such that the various portions of the pattern (lines (12), (14), (16) and (18)) are all maintained at the same electrical potential thereby preventing damage due to an electrostatic discharge.

Abstract: A nonvolatile memory cell such as an EPROM or EEPROM formed with a silicon on insulator technology has immunity to latchup and punchthrough and increased transconductance. A floating gate is formed atop a thin active layer of silicon containing source, drain and channel regions, the active layer lying atop an insulative layer that shields the active layer from an underlying silicon substrate. In a preferred embodiment, a stripe-shaped split gate extends over the floating gate and a portion of the channel, the split gate employed both to control charging and discharging of the floating gate and to sense whether charge is stored on the floating gate, while occupying a smaller memory cell area.

Abstract: A method of fabricating a micro-coaxial wiring structure comprises forming a first insulation layer and patterning a trench therein. A first conductive layer is formed on the first insulation layer and having a shape conforming to the insulation layer and lining the trench. A second insulation layer is formed on the first conductive layer within the trench and having a shape conforming to the first conductive layer lining the trench. A conductive signal line having a predetermined aspect ratio for providing a desired value of resistance per unit length is formed on the second insulation layer within the trench. A third insulation layer is then formed. Lastly, a conductive shielding line is formed upon the third insulation layer, the conductive shielding line being aligned with the conductive signal line.

Abstract: A method of depositing Ge on a Si substrate in a reaction chamber includes the steps of: precleaning the substrate; evacuating the chamber to a pressure below 10.sup.-7 Torr; heating the substrate to 300.degree.-600.degree. C.; and providing a GeH.sub.4 /B.sub.2 H.sub.6 /He mixture of gas with a GeH.sub.4 partial pressure of 2-50 mTorr and a B.sub.2 H.sub.6 partial pressure of 0.08 to 2 mTorr.

Abstract: A method of depositing Ge on a Si substrate in a reaction chamber includes the steps of: precleaning the substrate; evacuating the chamber to a pressure below 10.sup.-9 Torr; heating the substrate to 300-375 degrees C; and providing a 10% GeH4, 90% He mixture of gas with a GeH.sub.4 partial pressure of 1-5 mTorr.