Patents by Inventor Shailendra Srivastava

Shailendra Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220102179
    Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Zheng John Ye, Daemian Raj Benjamin Raj, Rana Howlader, Abhigyan Keshri, Sanjay G. Kamath, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Shailendra Srivastava, Kristopher R. Enslow, Xinhai Han, Deenesh Padhi, Edward P. Hammond
  • Publication number: 20220020570
    Abstract: Exemplary semiconductor processing systems may include a processing chamber including a lid stack having an output manifold. The systems may include a gas panel. The systems may include an input manifold. The input manifold may fluidly couple the gas panel with the output manifold of the processing chamber. A delivery line may extend from the input manifold to the output manifold. The systems may include a first transmission line extending from a first set of precursor sources of the gas panel to the delivery line. The systems may include a second transmission line extending from a second set of precursor sources of the gas panel to the delivery line. The second transmission line may be switchably coupled between the delivery line and an exhaust of the semiconductor processing system.
    Type: Application
    Filed: July 19, 2020
    Publication date: January 20, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Sai Susmita Addepalli, Yue Chen, Abhigyan Keshri, Qiang Ma, Zhijun Jiang, Shailendra Srivastava, Daemian Raj Benjamin Raj, Ganesh Balasubramanian
  • Publication number: 20210059037
    Abstract: A method and apparatus for controlling RF plasma attributes is disclosed. Some embodiments of the disclosure provide RF sensors within processing chambers operable at high temperatures. Some embodiments provide methods of measuring RF plasma attributes using RF sensors within a processing chamber to provide feedback control for an RF generator.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Zheng John Ye, Daemian Raj Benjamin Raj, Shailendra Srivastava, Nikhil Sudhindrarao Jorapur, Ndanka O. Mukuti, Dmitry A. Dzilno, Juan Carlos Rocha
  • Publication number: 20210047730
    Abstract: Exemplary semiconductor processing chambers may include a showerhead. The chambers may also include a substrate support characterized by a first surface facing the showerhead. The first surface may be configured to support a semiconductor substrate. The substrate support may define a recessed pocket centrally located within the first surface. The recessed pocket may be defined by an outer radial wall characterized by a height from the first surface within the recessed pocket that is greater than or about 150% of a thickness of the semiconductor substrate.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 18, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Sai Susmita Addepalli, Yue Chen, Zhijun Jiang, Shailendra Srivastava, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Greg Chichkanoff, Qiang Ma, Abhigyan Keshri, Xinhai Han, Ganesh Balasubramanian, Deenesh Padhi
  • Publication number: 20210035843
    Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.
    Type: Application
    Filed: July 22, 2020
    Publication date: February 4, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Jian Li, Juan C. Rocha, Zheng J. Ye, Daemian Raj Benjamin Raj, Shailendra Srivastava, Xinhai Han, Deenesh Padhi, Kesong Hu, Chuan-Ying Wang
  • Publication number: 20210003340
    Abstract: The present disclosure relates to a fluid delivery apparatus for deposition chambers. The fluid delivery device includes a fluid flow meter. The fluid flow meter is enclosed in an insulated box. An intake is provided on the insulated box for providing a forced cooling gas flow over the fluid flow meter. An exhaust is provided on the insulated box from which the forced cooling gas exits the insulated box.
    Type: Application
    Filed: March 14, 2019
    Publication date: January 7, 2021
    Inventors: Shailendra SRIVASTAVA, Seyed ALAM, Nikhil Sudhindrarao JORAPUR, Daemian Raj BENJAMIN RAJ, Juan Carlos ROCHA-ALVAREZ
  • Publication number: 20200385862
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 10, 2020
    Inventors: Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Daemian Raj BENJAMIN RAJ, Amit Kumar BANSAL, Juan Carlos ROCHA-ALVAREZ, Gregory Eugene CHICHKANOFF, Xinhai HAN, Masaki OGATA, Kristopher ENSLOW, Wenjiao WANG
  • Publication number: 20200365386
    Abstract: In one example, a process chamber comprises a lid assembly, a first gas supply, second gas supply, a chamber body, and a substrate support. The lid assembly comprises a gas box, a gas conduit passing through the gas box, a blocker plate, and a showerhead. The gas box comprises a gas distribution plenum, and a distribution plate comprising a plurality of holes aligned with the gas distribution plenum. The blocker plate is coupled to the gas box forming a first plenum. The showerhead is coupled to the blocker plate forming a second plenum. The first gas supply is coupled to the gas distribution plenum, and the second gas supply system is coupled to the gas conduit. The chamber body is coupled to the showerhead, and the substrate support assembly is disposed within an interior volume of the chamber body, and is configured to support a substrate during processing.
    Type: Application
    Filed: April 9, 2020
    Publication date: November 19, 2020
    Inventors: Daemian Raj BENJAMIN RAJ, Gregory Eugene CHICHKANOFF, Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Abhigyan KESHRI, Allison YAU
  • Publication number: 20200251311
    Abstract: Implementations disclosed herein generally relate to systems and methods of protecting a substrate support in a process chamber from cleaning fluid during a cleaning process. The method of cleaning the process chamber includes positioning in the process chamber a cover substrate above a substrate support and a process kit that separates a purge volume from a process volume. The method of cleaning includes flowing a purge gas in the purge volume to protect the substrate support and flowing a cleaning fluid to a process volume above the cover substrate, flowing the cleaning fluid in the process volume to an outer flow path, and to an exhaust outlet in the chamber body. The purge volume is maintained at a positive pressure with respect to the process volume to block the cleaning fluid from the purge volume.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Kalyanjit GHOSH, Shailendra SRIVASTAVA, Tejas ULAVI, Yusheng ZHOU, Amit Kumar BANSAL, Sanjeev BALUJA
  • Patent number: 10734237
    Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 4, 2020
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Lynford Goddard, Kaiyuan Wang, Chris Edwards, Lonna Edwards, Xin Yu, Gang Logan Liu, Samuel Washington, Shailendra Srivastava, Terry Koker, Julianne Lee, Catherine Britt Carlson
  • Publication number: 20200173022
    Abstract: Embodiments of the disclosure describe an apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 4, 2020
    Inventors: Xinhai HAN, Deenesh PADHI, Daemian Raj BENJAMIN RAJ, Kristopher ENSLOW, Wenjiao WANG, Masaki OGATA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Gregory Eugene CHICHKANOFF, Shailendra SRIVASTAVA, Jonghoon BAEK, Zakaria IBRAHIMI, Juan Carlos ROCHA-ALVAREZ, Tza-Jing GUNG
  • Patent number: 10636628
    Abstract: Implementations disclosed herein generally relate to systems and methods of protecting a substrate support in a process chamber from cleaning fluid during a cleaning process. The method of cleaning the process chamber includes positioning in the process chamber a cover substrate above a substrate support and a process kit that separates a purge volume from a process volume. The method of cleaning includes flowing a purge gas in the purge volume to protect the substrate support and flowing a cleaning fluid to a process volume above the cover substrate, flowing the cleaning fluid in the process volume to an outer flow path, and to an exhaust outlet in the chamber body. The purge volume is maintained at a positive pressure with respect to the process volume to block the cleaning fluid from the purge volume.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kalyanjit Ghosh, Shailendra Srivastava, Tejas Ulavi, Yusheng Zhou, Amit Kumar Bansal, Sanjeev Baluja
  • Patent number: 10600624
    Abstract: Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kalyanjit Ghosh, Sanjeev Baluja, Mayur G. Kulkarni, Shailendra Srivastava, Tejas Ulavi, Yusheng Alvin Zhou, Amit Kumar Bansal, Priyanka Dash, Zhijun Jiang, Ganesh Balasubramanian, Qiang Ma, Kaushik Alayavalli, Yuxing Zhang, Daniel Hwung, Shawyon Jafari
  • Publication number: 20190382889
    Abstract: Implementations of the present disclosure generally provide improved methods for cleaning a vacuum chamber to remove adsorbed contaminants therefrom prior to a chamber seasoning process while maintaining the chamber at desired deposition processing temperatures. The contaminants may be formed from the reaction of cleaning gases with the chamber components and the walls of the vacuum chamber.
    Type: Application
    Filed: May 24, 2019
    Publication date: December 19, 2019
    Inventors: Venkata Sharat Chandra PARIMI, Zhijun JIANG, Ganesh BALASUBRAMANIAN, Vivek Bharat SHAH, Shailendra SRIVASTAVA, Amit Kumar BANSAL, Xinhai HAN, Vinay K. PRABHAKAR
  • Publication number: 20190338420
    Abstract: Embodiments described herein relate to a pressure skew system for controlling the center-to-edge pressure change in a chamber for depositing an advanced patterning film with improved overall uniformity. The pressure skew system includes pumping zones configured to be formed in a chamber, walls disposed in the pumping region. The chamber includes a processing region, a pumping region, and a pumping path connected to a pump to exhaust process gases from the pumping region. Each pumping zone corresponds to a space of the pumping region flanked by the walls. Supply conduits are connected to a corresponding pumping zone and a corresponding mass flow control device to control a flow rate of inert gas provided to the corresponding pumping zone to control a pressure in an area of the processing region.
    Type: Application
    Filed: April 4, 2019
    Publication date: November 7, 2019
    Inventor: Shailendra SRIVASTAVA
  • Publication number: 20190122872
    Abstract: Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Kalyanjit GHOSH, Sanjeev BALUJA, Mayur G. KULKARNI, Shailendra SRIVASTAVA, Tejas ULAVI, Yusheng ALVIN ZHOU, Amit Kumar BANSAL, Priyanka DASH, Zhijun JIANG, Ganesh BALASUBRAMANIAN, Qiang MA, Kaushik ALAYAVALLI, Yuxing ZHANG, Daniel HWUNG, Shawyon JAFARI
  • Publication number: 20190080889
    Abstract: Implementations disclosed herein generally relate to systems and methods of protecting a substrate support in a process chamber from cleaning fluid during a cleaning process. The method of cleaning the process chamber includes positioning in the process chamber a cover substrate above a substrate support and a process kit that separates a purge volume from a process volume. The method of cleaning includes flowing a purge gas in the purge volume to protect the substrate support and flowing a cleaning fluid to a process volume above the cover substrate, flowing the cleaning fluid in the process volume to an outer flow path, and to an exhaust outlet in the chamber body. The purge volume is maintained at a positive pressure with respect to the process volume to block the cleaning fluid from the purge volume.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 14, 2019
    Inventors: Kalyanjit GHOSH, Shailendra SRIVASTAVA, Tejas ULAVI, Yusheng ZHOU, Amit Kumar BANSAL, Sanjeev BALUJA
  • Publication number: 20180301344
    Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 18, 2018
    Inventors: Lynford Goddard, Kaiyuan Wang, Chris Edwards, Lonna Edwards, Xin Yu, Gang Logan Liu, Samuel Washington, Shailendra Srivastava, Terry Koker, Julianne Lee, Catherine Britt Carlson
  • Publication number: 20160118265
    Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Lynford Goddard, Kaiyuan Wang, Chris Edwards, Lonna Edwards, Xin Yu, Gang Logan Liu, Samuel Washington, Shailendra Srivastava, Terry Koker, Julianne Lee, Catherine Britt Carlson
  • Patent number: 9148941
    Abstract: A first temperature distribution that represents a temperature of an element adjacent to and distinct from a first optical element that is positioned to receive an amplified light beam is accessed. The accessed first temperature distribution is analyzed to determine a temperature metric associated with the element, the determined temperature metric is compared to a baseline temperature metric, and an adjustment to position of the amplified light beam relative to the first optical element is determined based on the comparison.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: September 29, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Vladimir Fleurov, Igor Fomenkov, Shailendra Srivastava