Patents by Inventor Shane A. Hazzard
Shane A. Hazzard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946970Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.Type: GrantFiled: January 31, 2020Date of Patent: April 2, 2024Assignee: Tektronix, Inc.Inventors: Daniel S. Froelich, Shane A. Hazzard, Sarah R. Boen, Jed H. Andrews
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Publication number: 20220390513Abstract: An input selector for electrically connecting one of a plurality of test signals from a device under test to a test and measurement instrument includes a multiplexer having multiple inputs, each of the multiple inputs coupled to a different one of the plurality of test signals from the device under test, and having an output of a selected one of the multiple inputs, and an amplifier coupled to the output of the multiplexer for amplifying the selected test signal of the device under test before being sent as an output of the input selector to the test and measurement instrument. In alternative architectures, two or more amplifiers are coupled to the plurality of test signals, and the multiplexer selects an output of one of the two amplifiers to pass to a measurement instrument for testing.Type: ApplicationFiled: June 3, 2022Publication date: December 8, 2022Inventors: Shane A. Hazzard, Ajaiey Kumar Sharma, Timothy E. Bieber, John Marrinan, Andrew McCann, Pieter Christiaan Seidel, Josiah A. Bartlett
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Publication number: 20220034967Abstract: A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.Type: ApplicationFiled: July 14, 2021Publication date: February 3, 2022Applicant: Tektronix, Inc.Inventors: Sam J. Strickling, Daniel S. Froelich, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen, Shane A. Hazzard
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Publication number: 20200250368Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.Type: ApplicationFiled: January 31, 2020Publication date: August 6, 2020Inventors: Daniel S. Froelich, Shane A. Hazzard, Sarah R. Boen, Jed H. Andrews
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Publication number: 20200249275Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.Type: ApplicationFiled: January 31, 2020Publication date: August 6, 2020Inventors: Daniel S. Froelich, Shane A. Hazzard, Sarah R. Boen, Jed H. Andrews
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Patent number: 9934355Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.Type: GrantFiled: April 12, 2013Date of Patent: April 3, 2018Assignee: Tektronix, Inc.Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
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Patent number: 9075696Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.Type: GrantFiled: March 5, 2010Date of Patent: July 7, 2015Assignee: TEKTRONIX, INC.Inventors: Patrick A. Smith, David L. Kelly, Que Thuy Tran, Shane A. Hazzard
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Patent number: 8924175Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.Type: GrantFiled: April 12, 2013Date of Patent: December 30, 2014Assignee: Tektronix, Inc.Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
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Patent number: 8866468Abstract: A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.Type: GrantFiled: January 27, 2011Date of Patent: October 21, 2014Assignee: Tektronix, Inc.Inventors: Patrick A. Smith, Daniel G. Knierim, John C. Calvin, Shane A. Hazzard
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Publication number: 20130231883Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.Type: ApplicationFiled: April 12, 2013Publication date: September 5, 2013Applicant: Tektronix, Inc.Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
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Publication number: 20120194169Abstract: A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.Type: ApplicationFiled: January 27, 2011Publication date: August 2, 2012Applicant: TEKTRONIX, INC.Inventors: Patrick A. SMITH, Daniel G KNIERIM, John C. CALVIN, Shane A. HAZZARD
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Publication number: 20100228508Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.Type: ApplicationFiled: March 5, 2010Publication date: September 9, 2010Applicant: TEKTRONIX, INC.Inventors: Patrick A. SMITH, David L. KELLY, Que Thuy TRAN, Shane A. HAZZARD
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Patent number: 7652598Abstract: A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.Type: GrantFiled: October 26, 2007Date of Patent: January 26, 2010Assignee: Tektronix, Inc.Inventors: Shane A. Hazzard, Que Thuy Tran, Kayla R. Klingman, David L. Kelly, Patrick A. Smith, Daniel G. Knierim
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Publication number: 20090109071Abstract: A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: TEKTRONIX, INC.Inventors: Shane A. HAZZARD, Que Thuy TRAN, Kayla R. KLINGMAN, David L. KELLY, Patrick A. SMITH, Daniel G. KNIERIM