Abstract: In the disclosure, a display driver integrated circuit (DDIC) configured to drive a display panel and an electronic apparatus having the DDIC would generate display data to constantly update information displayed on the display panel even when a processor is in a power save mode. The DDIC includes a first input terminal, a memory device, an information rendering unit, an information overlay unit, and a source driver. The first input terminal receives a subscribed signal. The memory device stores a background image. The information rendering unit is coupled to the first input terminal of the DDIC to receive the subscribed signal and renders subscribed information according to the subscribed signal. The information overlay unit receives the subscribed information from the information overlay unit and the background image from the memory device, and accordingly, the display data is generated without obtaining frame data from an external processor.

Abstract: A charge pump including an output terminal, an external capacitor, and a switch module is provided. The output terminal is coupled to an internal capacitor disposed inside an integrated circuit (IC). The external capacitor is disposed outside the IC. The switch module, coupled to the external capacitor and the internal capacitor configured to control the external capacitor and the internal capacitor to charge and discharge by turns. In a first operating period, the switch module controls the external capacitor to charge without providing current to the output terminal, and controls the internal capacitor to discharge to the output terminal.

Abstract: A scan method for displaying image, wherein a display panel has N gate lines to display an image, and N?4. The image is displayed by dot inversion or line inversion. The method includes displaying a first image frame by a first scan sequence. The first frame has multiple first scan-line groups in relative darkness and multiple second scan-line groups in relative brightness, which are alternately displayed. Just after the second frame, a second scan sequence displays a second frame. The second frame has multiple first scan-line groups in relative darkness and multiple second scan-line groups in relative brightness, which are alternately displayed. The first and second scan-line groups of the first frame are complementary to the first and second scan-line groups of the second frame. The first scan-line groups of the first frame and second frame are relatively dark due to the pixels therein with insufficient charge.

Abstract: A driving method for a display device provides a first input pixel data corresponding to a pixel, and generates a second input pixel data by multiplying the first input pixel data by a predetermined rate. Next, an output pixel data corresponding to the second input pixel data is obtained from a predetermined gamma curve. When receiving the first input pixel data, the output pixel data is used for driving a display panel, and the second input pixel data is used for driving a backlight module of the display panel.

Abstract: A scan method for displaying image, wherein a display panel has N gate lines to display an image, and N?4. The image is displayed by dot inversion or line inversion. The method includes displaying a first image frame by a first scan sequence. The first frame has multiple first scan-line groups in relative darkness and multiple second scan-line groups in relative brightness, which are alternately displayed. Just after the second frame, a second scan sequence displays a second frame. The second frame has multiple first scan-line groups in relative darkness and multiple second scan-line groups in relative brightness, which are alternately displayed. The first and second scan-line groups of the first frame are complementary to the first and second scan-line groups of the second frame. The first scan-line groups of the first frame and second frame are relatively dark due to the pixels therein with insufficient charge.

Abstract: A gamma voltage generator including an operation amplifier, a first reference impedance unit, a second reference impedance unit, a first variable impedance unit, a second variable impedance unit, and a select unit is provided. The operation amplifier generates an amplified output voltage. The first reference impedance unit receives a first gamma voltage, and the second reference impedance unit receives a second gamma voltage. The first variable impedance unit provides a first variable impedance, and the second variable impedance unit receives the first gamma voltage and provides a second variable impedance. The select unit selects the amplified output voltage or the first gamma voltage according to a control signal to generate an interpolated gamma output voltage.

Abstract: A method for memory address arrangement is provided. Data of different Y coordinates is moved to operation units divided by different X coordinates, or data of different X coordinates is moved to operation units divided by different Y coordinates, so as to realize the function of simultaneously longitudinally and laterally reading and writing a plurality of batches of data, thereby preventing the limitation of only longitudinally or laterally reading and writing a plurality of batches of data.

Abstract: A charge pump including an output terminal, an external capacitor, and a switch module is provided. The output terminal is coupled to an internal capacitor disposed inside an integrated circuit (IC). The external capacitor is disposed outside the IC. The switch module, coupled to the external capacitor and the internal capacitor configured to control the external capacitor and the internal capacitor to charge and discharge by turns. In a first operating period, the switch module controls the external capacitor to charge without providing current to the output terminal, and controls the internal capacitor to discharge to the output terminal.

Abstract: An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a data output unit, a timing comparing controller and a comparing unit. The output terminal is coupled to the bidirectional bus and used for outputting a data output signal to the bidirectional bus. The input terminal is coupled to the output terminal and the bidirectional bus and used for receiving a data reception signal from the bidirectional bus. The data output unit is used for providing the data output signal. The timing comparing controller is used for generating a timing comparison signal according to the data output signal. The comparing unit is used for comparing the data reception signal with the data output signal according to the timing comparison signal to determine a contention state of the bidirectional bus.

Abstract: A power converting apparatus including a power converting unit and a control unit is provided. The power converting unit receives an input voltage and generates an output voltage for a display driving unit according to a control signal. The control unit provides the control signal to the power converting unit, wherein the control unit adjusts the duty cycle or the frequency of the control signal according to an image signal. In addition, a power converting method is also provided.

Abstract: A gamma voltage generation device for a flat panel display includes a first voltage dividing circuit coupled between a high voltage and a low voltage, for generating a plurality of primary voltages, a plurality of primary selectors coupled to the first voltage dividing circuit, each of the plurality of primary selectors for selecting a primary voltage from the plurality of primary voltages according to an original digital value, a second voltage dividing circuit coupled to the plurality of primary voltages, for generating a plurality of secondary voltages, and a plurality of secondary selectors coupled to the second voltage dividing circuit, each of the plurality of secondary selectors for selecting a secondary voltage to be a reference grayscale voltage of a gamma curve from a predetermined number of secondary voltages of the plurality of secondary voltages according to a target digital value.

Abstract: A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters boost the voltages of inputted signals to the voltages required by high voltage components and output the boosted signals. One of the first level shifters receives a first logic state and outputs a fifth logic state. Each of the other first level shifters receives a second logic state and outputs a sixth logic state. One of the second level shifters receives a third logic state and outputs a seventh logic state. Each of the other second level shifters receives a fourth logic state and outputs an eighth logic state. The demultiplexer outputs a ninth logic state and a plurality of tenth logic states according to the logic states outputted by the first level shifters and the second level shifters.

Abstract: A gamma voltage generator including an operation amplifier, a first reference impedance unit, a second reference impedance unit, a first variable impedance unit, a second variable impedance unit, and a select unit is provided. The operation amplifier generates an amplified output voltage. The first reference impedance unit receives a first gamma voltage, and the second reference impedance unit receives a second gamma voltage. The first variable impedance unit provides a first variable impedance, and the second variable impedance unit receives the first gamma voltage and provides a second variable impedance. The select unit selects the amplified output voltage or the first gamma voltage according to a control signal to generate an interpolated gamma output voltage.

Abstract: A driving method for a display device provides a first input pixel data corresponding to a pixel, and generates a second input pixel data by multiplying the first input pixel data by a predetermined rate. Next, an output pixel data corresponding to the second input pixel data is obtained from a predetermined gamma curve.

Abstract: An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a data output unit, a timing comparing controller and a comparing unit. The output terminal is coupled to the bidirectional bus and used for outputting a data output signal to the bidirectional bus. The input terminal is coupled to the output terminal and the bidirectional bus and used for receiving a data reception signal from the bidirectional bus. The data output unit is used for providing the data output signal. The timing comparing controller is used for generating a timing comparison signal according to the data output signal. The comparing unit is used for comparing the data reception signal with the data output signal according to the timing comparison signal to determine a contention state of the bidirectional bus.

Abstract: A method for memory address arrangement is provided. Data of different Y coordinates is moved to operation units divided by different X coordinates, or data of different X coordinates is moved to operation units divided by different Y coordinates, so as to realize the function of simultaneously longitudinally and laterally reading and writing a plurality of batches of data, thereby preventing the limitation of only longitudinally or laterally reading and writing a plurality of batches of data.

Abstract: A digital-to-analog converter (DAC) and the method thereof are disclosed. The DAC receives a digital signal with (M+N) bits, and a reference voltage unit sequentially outputs 2M+N reference voltages through the 2N output terminals thereof according to at least N timing signals. Afterwards, a control unit outputs at least a reference voltage to a decoding unit according to the above-mentioned N timing signals and the N bits of the digital signal. In the end, the decoding unit selects one of the signals produced by the control unit as the analog signal for output according to the M bits of the digital signal.

Abstract: A digital-to-analog converter (DA and the method thereof are disclosed. The DAC receives a digital signal with (M+N) bits, and a reference voltage unit sequentially outputs 2M+N reference voltages through the 2N output terminals thereof according to at least N timing signals. Afterwards, a control unit outputs at least a reference voltage to a decoding unit according to the above-mentioned N timing signals and the N bits of the digital signal. In the end, the decoding unit selects one of the signals produced by the control unit as the analog signal for output according to the M bits of the digital signal.

Abstract: A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters boost the voltages of inputted signals to the voltages required by high voltage components and output the boosted signals. One of the first level shifters receives a first logic state and outputs a fifth logic state. Each of the other first level shifters receives a second logic state and outputs a sixth logic state. One of the second level shifters receives a third logic state and outputs a seventh logic state. Each of the other second level shifters receives a fourth logic state and outputs an eighth logic state. The demultiplexer outputs a ninth logic state and a plurality of tenth logic states according to the logic states outputted by the first level shifters and the second level shifters.