Patents by Inventor Shang-Pin Chen

Shang-Pin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210295894
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Application
    Filed: April 22, 2021
    Publication date: September 23, 2021
    Applicant: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11017839
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 25, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • Patent number: 10932358
    Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 23, 2021
    Assignee: MediaTek Inc.
    Inventors: Duen-Yi Ho, Hung-Chuan Chen, Shang-Pin Chen
  • Patent number: 10846018
    Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Shang-Pin Chen
  • Publication number: 20200051615
    Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.
    Type: Application
    Filed: October 20, 2019
    Publication date: February 13, 2020
    Inventors: Chung-Hwa Wu, Shang-Pin Chen
  • Publication number: 20190098747
    Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 28, 2019
    Inventors: Duen-Yi HO, Hung-Chuan CHEN, Shang-Pin CHEN
  • Patent number: 10163485
    Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 10141044
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 27, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Publication number: 20180322914
    Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.
    Type: Application
    Filed: April 23, 2018
    Publication date: November 8, 2018
    Inventors: Chung-Hwa Wu, Shang-Pin Chen
  • Patent number: 10109341
    Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 23, 2018
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Shang-Pin Chen
  • Publication number: 20180293026
    Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.
    Type: Application
    Filed: March 26, 2018
    Publication date: October 11, 2018
    Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Shang-Pin CHEN
  • Patent number: 10083728
    Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.
    Type: Grant
    Filed: July 6, 2014
    Date of Patent: September 25, 2018
    Assignee: MediaTek Inc.
    Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Pin Chen
  • Patent number: 10037952
    Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 31, 2018
    Assignee: MediaTek Inc.
    Inventors: Chun-Wei Chang, Shang-Pin Chen
  • Publication number: 20180204610
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 19, 2018
    Inventors: Bo-Wei HSIEH, Ching-Yeh HSUAN, Shang-Pin CHEN
  • Patent number: 9871518
    Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Patent number: 9859900
    Abstract: A jitter control circuit within a chip comprises an adaptive PDN, a current generator and a jitter generator. The adaptive PDN is capable of being controlled/modulated to provide difference impedances. The current generator is coupled to the adaptive PDN, and is arranged for receiving a supply voltage provided by the adaptive PDN and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN, and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 2, 2018
    Assignee: MediaTek Inc.
    Inventors: Shang-Pin Chen, Sheng-Feng Lee
  • Publication number: 20170345480
    Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
    Type: Application
    Filed: April 6, 2017
    Publication date: November 30, 2017
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 9829914
    Abstract: A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 28, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 9824728
    Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 21, 2017
    Assignee: MediaTek Inc.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh