Patents by Inventor Shang-Pin Chen

Shang-Pin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9812187
    Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.
    Type: Grant
    Filed: February 5, 2017
    Date of Patent: November 7, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Publication number: 20170243629
    Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.
    Type: Application
    Filed: February 5, 2017
    Publication date: August 24, 2017
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Publication number: 20170243628
    Abstract: A memory system includes a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module includes a termination module, and the first clock signal is coupled to the inverted first clock signal through the termination module.
    Type: Application
    Filed: December 26, 2016
    Publication date: August 24, 2017
    Inventor: Shang-Pin Chen
  • Publication number: 20170221544
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Application
    Filed: August 25, 2016
    Publication date: August 3, 2017
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Publication number: 20170222647
    Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
    Type: Application
    Filed: August 25, 2016
    Publication date: August 3, 2017
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Publication number: 20170147030
    Abstract: A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Publication number: 20170133078
    Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 11, 2017
    Inventors: Bo-Wei Hsieh, Shang-Pin Chen
  • Publication number: 20170125363
    Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.
    Type: Application
    Filed: January 18, 2017
    Publication date: May 4, 2017
    Inventors: Chun-Wei CHANG, Shang-Pin CHEN
  • Patent number: 9613665
    Abstract: A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: April 4, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 9608624
    Abstract: An apparatus for performing signal driving with aid of MOSFET and an associated IC are provided, where the apparatus includes a PMOSFET coupled between a predetermined voltage level and a terminal, and further includes an NMOSFET coupled between the predetermined voltage level and the terminal. The PMOSFET is arranged for selectively driving a signal that passes through the terminal. In addition, the NMOSFET is arranged for selectively driving the signal. Additionally, the apparatus further includes another NMOSFET coupled between another predetermined voltage level and the terminal, wherein the other NMOSFET is arranged for selectively driving the signal. More particularly, the PMOSFET, the NMOSFET, and the other NMOSFET does not drive the signal at the same time. For example, each of the PMOSFET, the NMOSFET, and the other NMOSFET selectively drives the signal to have one of a plurality of logical states.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 28, 2017
    Assignee: MEDIATEK INC.
    Inventor: Shang-Pin Chen
  • Publication number: 20170040995
    Abstract: An apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.
    Type: Application
    Filed: June 16, 2016
    Publication date: February 9, 2017
    Inventors: An-Siou Li, Shang-Pin Chen
  • Patent number: 9525294
    Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 20, 2016
    Assignee: MEDIATEK INC.
    Inventors: Hao-Ping Hong, Shang-Pin Chen, Ding-Shiuan Shen
  • Publication number: 20160359488
    Abstract: A jitter control circuit within a chip comprises an adaptive PDN, a current generator and a jitter generator. The adaptive PDN is capable of being controlled/modulated to provide difference impedances. The current generator is coupled to the adaptive PDN, and is arranged for receiving a supply voltage provided by the adaptive PDN and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN, and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN.
    Type: Application
    Filed: April 6, 2016
    Publication date: December 8, 2016
    Inventors: Shang-Pin Chen, Sheng-Feng Lee
  • Patent number: 9473142
    Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 18, 2016
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, An-Siou Li
  • Publication number: 20160233710
    Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Hao-Ping Hong, Shang-Pin Chen, Ding-Shiuan Shen
  • Publication number: 20160173082
    Abstract: A method and apparatus for performing impedance profile control of a power delivery network (PDN) in an electronic device are provided. The method includes the steps of: utilizing a capacitive component and a resistive component that are coupled in series as an output stage of the PDN, wherein the capacitive component includes one terminal coupled to a first voltage level of the PDN and further includes another terminal, and the resistive component includes a first terminal coupled to the other terminal of the capacitive component and further includes a second terminal coupled to a second voltage level of the PDN; and inputting a control signal into a third terminal of the resistive component, to control an impedance profile of the output stage of the PDN, wherein in a predetermined state of the control signal, the control signal is a time variant signal. The control signal may be digital or analog.
    Type: Application
    Filed: August 20, 2015
    Publication date: June 16, 2016
    Inventors: Shang-Pin Chen, Sheng-Feng Lee
  • Publication number: 20160173093
    Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.
    Type: Application
    Filed: August 20, 2015
    Publication date: June 16, 2016
    Inventors: Shang-Pin Chen, An-Siou Li
  • Publication number: 20150256173
    Abstract: An apparatus for performing signal driving with aid of MOSFET and an associated IC are provided, where the apparatus includes a PMOSFET coupled between a predetermined voltage level and a terminal, and further includes an NMOSFET coupled between the predetermined voltage level and the terminal. The PMOSFET is arranged for selectively driving a signal that passes through the terminal. In addition, the NMOSFET is arranged for selectively driving the signal. Additionally, the apparatus further includes another NMOSFET coupled between another predetermined voltage level and the terminal, wherein the other NMOSFET is arranged for selectively driving the signal. More particularly, the PMOSFET, the NMOSFET, and the other NMOSFET does not drive the signal at the same time. For example, each of the PMOSFET, the NMOSFET, and the other NMOSFET selectively drives the signal to have one of a plurality of logical states.
    Type: Application
    Filed: November 21, 2014
    Publication date: September 10, 2015
    Inventor: Shang-Pin Chen
  • Publication number: 20150255129
    Abstract: A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift.
    Type: Application
    Filed: November 6, 2014
    Publication date: September 10, 2015
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Publication number: 20150170719
    Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.
    Type: Application
    Filed: June 2, 2014
    Publication date: June 18, 2015
    Applicant: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh