Patents by Inventor Shang-Wen Chang

Shang-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081403
    Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11075195
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Patent number: 11063041
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20210202465
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans D1 along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<D1; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Publication number: 20210202385
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
    Type: Application
    Filed: July 30, 2020
    Publication date: July 1, 2021
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11004738
    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 11, 2021
    Inventors: Yi-Hsiung Lin, Yu-Xuan Huang, Chih-Ming Lai, Ru-Gun Liu, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20210066291
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10879176
    Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20200294860
    Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Wen CHANG, Yi-Hsiung LIN, Yi-Hsun CHIU
  • Patent number: 10672665
    Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
  • Publication number: 20200135724
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Yi-Hsiung Lin, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20200135644
    Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.
    Type: Application
    Filed: January 18, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung LIN, Shang-Wen CHANG, Yi-Hsun CHIU
  • Patent number: 10614908
    Abstract: A method for fixing outlier bits is provided in the invention. The method is applied to a memory device, and a memory array of the memory device is divided into a plurality of blocks. The method includes the steps of setting an initial voltage and a terminal voltage of a margin read (MGRD) operation in each block, wherein the initial voltage is set in a distribution of a threshold voltage of each block; finding a MGRD spec corresponding to each block at a range defined by the initial voltage and the terminal voltage; detecting outlier bits in each block according to the MGRD spec corresponding to each block; and fixing the outlier bits in each block.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 7, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Shang-Rong Wu, Shang-Wen Chang
  • Publication number: 20200105603
    Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
    Type: Application
    Filed: January 18, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Wen CHANG, Yi-Hsiung LIN, Yi-Hsun CHIU
  • Publication number: 20200098764
    Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.
    Type: Application
    Filed: July 30, 2019
    Publication date: March 26, 2020
    Inventors: Chih-Hao Wang, Yi-Hsun Chiu, Yi-Hsiung Lin, Shang-Wen Chang
  • Publication number: 20200098631
    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.
    Type: Application
    Filed: August 5, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Yu-Xuan Huang, Chih-Ming Lai, Ru-Gun Liu, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20200020584
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 16, 2020
    Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG
  • Publication number: 20200006160
    Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.
    Type: Application
    Filed: April 24, 2019
    Publication date: January 2, 2020
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Publication number: 20190348142
    Abstract: A method for fixing outlier bits is provided in the invention. The method is applied to a memory device, and a memory array of the memory device is divided into a plurality of blocks. The method includes the steps of setting an initial voltage and a terminal voltage of a margin read (MGRD) operation in each block, wherein the initial voltage is set in a distribution of a threshold voltage of each block; finding a MGRD spec corresponding to each block at a range defined by the initial voltage and the terminal voltage; detecting outlier bits in each block according to the MGRD spec corresponding to each block; and fixing the outlier bits in each block.
    Type: Application
    Filed: March 6, 2019
    Publication date: November 14, 2019
    Inventors: Shang-Rong WU, Shang-Wen CHANG
  • Patent number: 10431312
    Abstract: A non-volatile memory apparatus and a refresh method thereof are provided. A control circuit determines whether threshold voltages of memory cells in a memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, and the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Im-Cheol Ha, Shang-Wen Chang