Patents by Inventor Shang-Yun Tu

Shang-Yun Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149141
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11239305
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11152273
    Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20210028266
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: January 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Publication number: 20200243410
    Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Patent number: 10629509
    Abstract: Redistribution circuit structures and methods of forming the same are disclosed. One of the redistribution circuit structures includes a first conductive structure, a dielectric layer and a second conductive structure. The dielectric layer is disposed over and exposes a portion of the first conductive structure. The second conductive structure is disposed in the dielectric layer to electrically connect to the first conductive structure, and includes a first conductive layer and a second conductive layer disposed on and electrically connected to the first conductive layer. The first conductive layer includes a main portion and a conductive protrusion, the conductive protrusion is disposed on an entire edge of an upper surface of the main portion, and a top of the conductive protrusion is higher than the upper surface of the main portion.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20190131200
    Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Patent number: 10037973
    Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 9991218
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20170229413
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9659903
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20160336298
    Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 17, 2016
    Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG
  • Publication number: 20160268227
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9406629
    Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 9373598
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20160111384
    Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG
  • Publication number: 20150303160
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 22, 2015
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9093440
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20140231987
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Application
    Filed: April 24, 2014
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 8729699
    Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Yao-Chun Chuang, Ming Hung Tseng, Chen-Cheng Kuo, Chen-Shien Chen