Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract: A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional execution instruction specifies one or more instructions to be conditionally executed (i.e., “target instructions”), a register of the processor, and a condition within the register. When the instruction unit fetches and decodes the conditional execution instruction, the execution unit saves results of the one or more target instructions dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction. A system including the processor is described, as is a method for conditionally executing at least one instruction.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit.

Abstract: A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may provide zero-overhead looping for branch instructions, in addition to single loop constructs and multiple loop constructs (which may or may not be nested). Zero-overhead looping may also be provided in special cases, e.g., when servicing an interrupt or executing a branch-out-of-loop instruction. In addition to reducing the number of instructions required to execute a program, as well as the overall time and power consumed during program execution, the hardware looping mechanism described herein may be integrated within any processor architecture without modifying existing program code.

Abstract: For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.

Abstract: A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism including: (1) a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage and (2) out-of-order completion logic, associated with the MAC, that causes interim results produced by the multiply stage to be stored when the accumulate stage is unavailable and allows younger instructions to complete before the multiply-accumulate instructions.

Abstract: A disclosed processor includes update logic coupled to a register. The update logic receives a first signal indicative of a first add-compare-select (ACS) instruction result and a second signal indicative of a second ACS instruction result, and updates the contents of the register dependent upon the first and second signals. In the event the first and second signals are received substantially simultaneously, the update logic shifts the contents of the register 2 bit positions in order thereby vacating 2 consecutive bit positions, updates one of the vacated bit positions dependent upon the first signal, and updates the other vacated bit position dependent upon the second signal. A described method for decoding convolutional code includes generating computer program code for a processor including two or more ACS instructions. Storage elements specified by each of the ACS instructions are selected such that the processor can execute the ACS instructions substantially simultaneously.

Abstract: A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors.

Abstract: A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the processor drives the user-defined address or command upon one or more signal lines of the bus via the bus interface during execution of the instruction. A described data processing system includes the processor coupled to a device including an addressable register. The device receives a user-defined address from the processor and accesses the addressable register in response to the user-defined address. Methods are disclosed for obtaining a value stored in an addressable register, providing a value stored in an addressable register, storing a value in an addressable register, and modifying a value stored in an addressable register.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit.

Abstract: A system for, and method of, reference-modeling a processor design. In one embodiment, the system includes: (1) an architecture database that contains specifications regarding the processor design that include: instruction set specifications, architectural resource specifications, pipeline specifications and connectivity specifications, (2) a simulation subsystem that draws selected portions of the specifications to simulate and test the processor design and (3) a documentation subsystem that draws other selected portions of the specifications to document and register-model the processor design, changes in the specifications being propagated to the architecture database.

Abstract: An improved method of operating a digital signal processor instruction pipeline and a memory interface for implementing the method. Memory store requests are separated into an address phase and a data phase. Store addresses are issued to the interface when ready and held in a queue until the corresponding store data is available. The store data is issued to the interface and held in a queue until its corresponding store address is to be coupled to memory. The pipeline operates more efficiently because it does not have to wait for store data before issuing the address and related control signals. Data coherency is maintained because load and store addresses are issued at the same pipeline stage and executed in the order issued.

Abstract: An instruction pipeline for a DSP with fusing logic for combining multiple instructions into a single control word which can be executed by one execution unit. The pipeline fetches a greater number of instructions than the number of execution units to which it can issue instructions. It applies grouping rules to the instructions and also identifies pairs, or larger groups, of instructions which can be combined, or fused, into a single control word which can be executed by one execution unit. Issuance of a fused control word to a single execution unit effectively allows two or more instructions to be executed simultaneously in one execution unit.

Abstract: A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the processor drives the user-defined address or command upon one or more signal lines of the bus via the bus interface during execution of the instruction. A described data processing system includes the processor coupled to a device including an addressable register. The device receives a user-defined address from the processor and accesses the addressable register in response to the user-defined address. Methods are disclosed for obtaining a value stored in an addressable register, providing a value stored in an addressable register, storing a value in an addressable register, and modifying a value stored in an addressable register.

Abstract: A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors.

Abstract: A disclosed processor includes update logic coupled to a register. The update logic receives a first signal indicative of a first add-compare-select (ACS) instruction result and a second signal indicative of a second ACS instruction result, and updates the contents of the register dependent upon the first and second signals. In the event the first and second signals are received substantially simultaneously, the update logic shifts the contents of the register 2 bit positions in order thereby vacating 2 consecutive bit positions, updates one of the vacated bit positions dependent upon the first signal, and updates the other vacated bit position dependent upon the second signal. A described method for decoding convolutional code includes generating computer program code for a processor including two or more ACS instructions. Storage elements specified by each of the ACS instructions are selected such that the processor can execute the ACS instructions substantially simultaneously.

Abstract: A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit.

Abstract: A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes a conditional execution instruction and one or more target instructions. The conditional execution instruction specifies the target instructions, a register, and a register condition, and includes pointer update information. The execution unit saves a result of each of the target instructions dependent upon the existence of the specified register condition during execution of the conditional execution instruction. When a target instruction is an instruction involving a pointer subject to update, the execution unit updates the pointer dependent upon the pointer update information. A system (e.g., a computer system) is described including the processor coupled to a memory system. A method is disclosed for conditionally executing at least one instruction, including inputting the conditional execution instruction and the target instructions.