Patents by Inventor Shao-Chang Huang

Shao-Chang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050224883
    Abstract: A charge device model (CDM) immunity module used in a semiconductor circuit for CDM damage protection. The CDM immunity module comprises a CDM ground pad and a current directing device such as a diode coupled between the CDM ground pad and a substrate of at least one device in a core circuit to be protected, wherein the current directing device and the CDM ground pad dissipate CDM charges to avoid damage to an oxide layer of the protected device.
    Type: Application
    Filed: April 6, 2004
    Publication date: October 13, 2005
    Inventors: Shao-Chang Huang, Shu-Chuan Lee
  • Patent number: 6927457
    Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 9, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Chang Huang, Jin-Tau Chou
  • Publication number: 20040212015
    Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 28, 2004
    Inventors: Shao-Chang Huang, Jin-Tau Chou
  • Patent number: 6768619
    Abstract: A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: July 27, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang
  • Patent number: 6762466
    Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: July 13, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Chang Huang, Jin-Tau Chou
  • Patent number: 6671147
    Abstract: A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: December 30, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang
  • Publication number: 20030193071
    Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.
    Type: Application
    Filed: April 11, 2002
    Publication date: October 16, 2003
    Inventors: Shao-Chang Huang, Jin-Tau Chou
  • Publication number: 20030122192
    Abstract: A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region.
    Type: Application
    Filed: February 13, 2003
    Publication date: July 3, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang
  • Patent number: 6573566
    Abstract: A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: June 3, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang
  • Publication number: 20030007301
    Abstract: A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region.
    Type: Application
    Filed: July 9, 2001
    Publication date: January 9, 2003
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang
  • Publication number: 20020167053
    Abstract: A CDM protection is provided within an internal device region of an integrated circuit where a plurality of working components are formed. The CDM protection circuit comprises a plurality of CDM protection devices that are electrically connected to one another, and a grounded conductive pad electrically connected to one CDM protection device, the CDM protection devices including a plurality of dummy devices such as dummy metals in tapered shape. The CDM protection devices are distributed over the internal device region in a manner to achieve a global protection of the IC against CDM charges by absorbing and dissipating the CDM charges. To increase CDM protection, a capacitor is further disposed in a manner to surround the internal device region.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 14, 2002
    Inventor: Shao-Chang Huang
  • Publication number: 20020154462
    Abstract: A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current.
    Type: Application
    Filed: June 1, 2001
    Publication date: October 24, 2002
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Shao-Chang Huang