Patents by Inventor Shariq Siddiqui
Shariq Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11062083Abstract: Disclosed are various embodiments for optimizing automated data entry by recognizing invalid data items and providing alternatives. An electronic form that requests a plurality of data items is received. The data items are automatically provided to the electronic form using stored data and/or automatically generated data. It is automatically detected that a particular data item is deemed invalid for the electronic form. In various embodiments, a suggestion for providing a valid data item may be extracted from the electronic form. An alternative data item is then automatically provided to the electronic form in place of the particular data item based at least in part on the suggestion.Type: GrantFiled: December 9, 2015Date of Patent: July 13, 2021Assignee: Amazon Technologies, Inc.Inventors: Daniel Wade Hitchcock, Shariq Siddiqui
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Patent number: 10957588Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: October 25, 2016Date of Patent: March 23, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10937694Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: July 5, 2019Date of Patent: March 2, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10903118Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: July 5, 2019Date of Patent: January 26, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10818599Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.Type: GrantFiled: January 1, 2019Date of Patent: October 27, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
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Publication number: 20200169552Abstract: Disclosed are various embodiments for using an audio interface device to facilitate authentication for other devices. A client device presents an authentication code via an output device of the client device. The authentication code is received from a voice interface device. The voice interface device is in an authenticated state for access to an account, and the voice interface device received the authentication code from speech captured by a microphone of the voice interface device following a spoken wake word. The client device is authenticated for access to the account in response to determining that the authentication code received from the voice interface device matches the authentication code presented by the client device.Type: ApplicationFiled: January 29, 2020Publication date: May 28, 2020Inventors: SHARIQ SIDDIQUI, DANIEL WADE HITCHCOCK, BHARATH KUMAR BHIMANAIK, NATALIE NGUYEN, ANNABELLE RICHARD BACKMAN
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Patent number: 10658176Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.Type: GrantFiled: September 6, 2018Date of Patent: May 19, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
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Patent number: 10629428Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.Type: GrantFiled: March 9, 2018Date of Patent: April 21, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Shariq Siddiqui, Han You, Xunyuan Zhang, Rohit Galatage, Roger A. Quon, Christopher J. Penny
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Publication number: 20200083040Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
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Patent number: 10554657Abstract: Disclosed are various embodiments for using an audio interface device to facilitate authentication for other devices. An authentication service causes a first client device to present an authentication code via an output device of the first client device. The authentication service receives the authentication code from a second client device. The second client device is in an authenticated state for access to an account, and the second client device received the authentication code from an environmental sensor while in a listening mode. The authentication service authenticates the first client device for access to the account in response to determining that the authentication code received from the second client device matches the authentication code presented by the first client device.Type: GrantFiled: July 31, 2017Date of Patent: February 4, 2020Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Shariq Siddiqui, Daniel Wade Hitchcock, Bharath Kumar Bhimanaik, Natalie Nguyen, Annabelle Richard Backman
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Publication number: 20190333814Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Mark L. LENHARDT, Frank W. MONT, Brown C. PEETHALA, Shariq SIDDIQUI, Jessica P. STRISS, Douglas M. TRICKETT
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Publication number: 20190333813Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Mark L. LENHARDT, Frank W. MONT, Brown C. PEETHALA, Shariq SIDDIQUI, Jessica P. STRISS, Douglas M. TRICKETT
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Publication number: 20190279860Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Inventors: Shariq SIDDIQUI, Han YOU, Xunyuan ZHANG, Rohit GALATAGE, Roger A. QUON, Christopher J. PENNY
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Patent number: 10388565Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.Type: GrantFiled: May 17, 2018Date of Patent: August 20, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
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Patent number: 10347541Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.Type: GrantFiled: April 25, 2018Date of Patent: July 9, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, David Paul Brunco, Pei Liu, Shariq Siddiqui, Jinping Liu
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Patent number: 10340146Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.Type: GrantFiled: July 12, 2017Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Rohit Galatage, Shariq Siddiqui, Chung-Ju Yang
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Publication number: 20190157413Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.Type: ApplicationFiled: January 1, 2019Publication date: May 23, 2019Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
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Patent number: 10211094Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.Type: GrantFiled: July 5, 2017Date of Patent: February 19, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
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Publication number: 20190019682Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Rohit Galatage, Shariq Siddiqui, Chung-Ju Yang
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Patent number: 10170574Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.Type: GrantFiled: October 24, 2017Date of Patent: January 1, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita