Patents by Inventor Shay REBOH

Shay REBOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234573
    Abstract: A FET microelectronic device comprising: a semiconductor layer a first area of which forms a channel; a gate and a gate dielectric layer or a ferroelectric memory layer, arranged against the first area; dielectric spacers arranged against sidewalls of the gate; source/drain regions electrically coupled to the first area via second areas of the active layer extending between the source/drain regions and the dielectric spacers; wherein the second areas form a continuous layer with the first area, and the first area forms a semiconductor portion such that the gate covers several distinct faces of the semiconductor portion.
    Type: Application
    Filed: December 21, 2023
    Publication date: July 11, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Rémi COQUAND, Shay REBOH
  • Patent number: 12027421
    Abstract: A method for creating a substrate of the semiconductor on insulator type includes steps of a) providing a donor substrate having a monocrystalline support substrate, a smoothing layer and a semiconductor layer, the smoothing layer forming an etch stop layer with respect to the material of the support substrate; a?) implantation of ion species through the semiconductor layer to form a fragilisation plane; b) creating an assembly by placing the donor substrate and a receiver substrate in contact; and c) transferring the semiconductor layer and at least a part of the smoothing layer by detachment along the fragilization plane. The semiconductor layer provided in a) is monocrystalline. The method may further include, before b), amorphization of at least a part of the semiconductor layer to form an amorphous layer; and during or after c), recrystallization in solid phase of the amorphous layer to form a transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: July 2, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay Reboh
  • Publication number: 20240215263
    Abstract: A memory device (100) comprising at least one memory stack (158) electrically connected in series with a selection transistor, comprising: a semiconductor layer (120) first areas (122) of which are superimposed and form a channel; an electrostatic control gate (110) and a gate dielectric layer (112) such that parts of the gate dielectric layer are each arranged between a part (106, 108) of the gate and one of the first areas; dielectric spacers (114) arranged against sidewalls of the gate; contact regions (116, 118) electrically coupled to the first areas via second areas (124) of the semiconductor layer extending between the contact regions and the spacers, one of the contact regions (118) comprising the memory stack; and wherein the second areas form a continuous layer with the first areas.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 27, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Rémi COQUAND, Shay REBOH
  • Publication number: 20240213359
    Abstract: A microelectronic device comprising: a semiconductor layer (120) several first areas (122) of which are superposed and form a channel; an electrostatic control gate (110) and a gate dielectric layer (112) or a ferroelectric memory layer (112) parts of which are each arranged between a part (106, 108) of the gate and one amongst the first areas; dielectric spacers (114) arranged against sidewalls of the gate; source (116)/drain (118) regions electrically coupled to the first areas by second areas (124) of the semiconductor layer extending between the source/drain regions and the spacers, and/or between a substrate (102) and each of the source/drain regions; and wherein the second areas are not arranged directly against the layer and form a continuous layer with the first areas.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 27, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Rémi COQUAND, Shay REBOH
  • Publication number: 20240203735
    Abstract: A method for producing a transistor comprising: providing on a support provided with a surface semiconductor layer and resting on an insulating layer: a gate block, insulating spacers on either side of this gate block, and so-called raised semiconductor regions, making amorphous the raised semiconductor regions and the portions of the superficial semiconductor layer located under these raised semiconductor regions and reaching the insulating layer, doping the raised semiconductor regions and said portions, carrying out a laser heat annealing by means of one or more laser pulses so as to produce a recrystallisation of said raised regions and of said portions while carrying out an activation of dopants in said regions and said portions.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 20, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Pablo ACOSTA ALBA, Frédéric MILESI
  • Publication number: 20240194485
    Abstract: A method for manufacturing a field effect transistor including a silicon-germanium active layer and a gate oxide layer disposed on the active layer, the method including providing a stack including a substrate and a silicon-germanium first layer disposed on the substrate; forming the gate oxide layer on the stack; subjecting the stack to laser annealing so as to melt a region of the stack, the region including at least one part of the first layer, and recrystallising the molten region of the stack to obtain the silicon-germanium active layer in contact with the gate oxide layer, the active layer having a germanium concentration gradient.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 13, 2024
    Inventors: Pablo ACOSTA ALBA, Claire FENOUILLET-BERANGER, Rémy GASSILLOUD, Sébastien KERDILES, Shay REBOH
  • Publication number: 20240194539
    Abstract: A method for manufacturing a semiconductor device including a first semiconductor zone optimised for electron conduction and a second semiconductor zone optimised for hole conduction, the method including providing a multilayer structure including a substrate and a silicon-germanium layer disposed on the substrate; defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone, and subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region, the portion including prior to laser annealing a part of the silicon-germanium layer, the portion having after laser annealing a germanium concentration gradient with a germanium concentration which increases towards an upper face of the portion.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 13, 2024
    Inventors: Pablo ACOSTA ALBA, Shay REBOH
  • Publication number: 20240194538
    Abstract: A method for manufacturing a semiconductor device including a first semiconductor zone optimised for electron conduction and a second semiconductor zone optimised for hole conduction, the method including providing a multilayer structure including a substrate and a silicon-germanium layer disposed on the substrate; defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone; subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the first region, the portion including prior to laser annealing a part of the silicon-germanium layer, the portion including after the laser annealing a germanium-depleted part and a germanium-enriched part disposed on the germanium-depleted part, and etching the germanium-enriched part so as to expose the germanium-depleted part.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 13, 2024
    Inventors: Pablo ACOSTA ALBA, Shay REBOH
  • Publication number: 20240154036
    Abstract: Stack of layers of monocrystalline materials suitable for producing microelectronic devices with 3D architecture comprising transistors, including several first layers of monocrystalline material, several second layers of monocrystalline material different from that of the first layers, and at least one third layer of monocrystalline material different from those of the first and second layers, wherein: a first of the monocrystalline materials of the first, second and third layers corresponds to intrinsic silicon; a second of the monocrystalline materials of the first, second and third layers corresponds to intrinsic SiGe; a third of the monocrystalline materials of the first, second and third layers corresponds to p-doped silicon or p-doped SiGe.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 9, 2024
    Inventors: Sylvain Barraud, Shay Reboh
  • Patent number: 11967633
    Abstract: A method for forming at least one doped region of a transistor includes providing a stack having an insulating layer, an active layer, and a gate pattern having a first lateral flank and removing a first portion of the active layer not overlaid by the gate pattern and extending down to the gate pattern, at the edge of a second portion of the active layer overlaid by the gate pattern, so as to expose an edge of the second portion. The edge extends substantially in a continuation of the lateral flank of the gate pattern. The method also includes forming a first spacer having an L shape and having a basal portion in contact with the insulating layer and a lateral portion in contact with the lateral flank; forming a second spacer on the first spacer; removing the basal portion of the first spacer by selective etching with respect to the second spacer, so as to expose the edge of the second portion; and forming the doped region by epitaxy from the exposed edge.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 23, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay Reboh
  • Patent number: 11942323
    Abstract: A method for forming a doped zone of a transistor includes providing a stack having at least one active layer made from a semiconductor material, and a transistor gate pattern having at least one lateral side, and modifying a portion of the active layer so as to form a modified portion made of a modified semiconductor material. The modified portion extends down to the at least one lateral side of the gate pattern, at the edge of a non-modified portion above which the gate pattern is located. The method also includes forming a spacer on the lateral side, removing the modified portion by selective etching of the modified semiconductor material with respect to the semiconductor material of the non-modified portion, so as to expose an edge of the non-modified portion, and forming the doped zone by epitaxy starting from the exposed edge.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay Reboh
  • Patent number: 11901194
    Abstract: The invention relates to a method for forming a porous portion in a substrate, an implantation of ions in at least one region of a layer, for example based on a semiconductor material, so as to form a portion enriched with at least one gas in the implanted region, and then a laser annealing of the nanosecond type so as to form a porous portion. The use of the ion implantation makes it possible to dissociate the deposition of the layer based on semiconductor material from the incorporation of gas. A great variety of porous structures can be obtained by the method. These porous structures can be adapted for numerous applications according to the properties sought.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 13, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Pablo Acosta Alba
  • Publication number: 20240030061
    Abstract: A donor substrate for transferring a single-crystal thin layer made of a first material, onto a receiver substrate. The donor substrate comprises: —a buried weakened plane delimiting an upper portion and a lower portion of the donor substrate, —in the upper portion, a first layer, a second layer adjacent to the buried weakened plane, and a stop layer between the first layer and the second layer the first layer composed of the first material, the stop layer being formed of a second material, —an amorphized sub-portion, made amorphous by ion implantation, having a thickness less than that of the upper portion, and including at least the first layer; the second layer comprising at least one single-crystal sub-layer, adjacent to the buried weakened plane. Two embodiments of a method may be used for transferring a single-crystal thin layer from the donor substrate.
    Type: Application
    Filed: November 19, 2021
    Publication date: January 25, 2024
    Inventors: Larry Vincent, Shay Reboh, Lucie Le Van-Jodin, Frédéric Milesi, Ludovic Ecarnot, Gweltaz Gaudin, Didier Landru
  • Patent number: 11848191
    Abstract: Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: December 19, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland
  • Patent number: 11810789
    Abstract: A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 7, 2023
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay Reboh, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
  • Patent number: 11769687
    Abstract: A method for transferring a thin layer from a donor substrate to a receiver substrate including the steps of implantation of species carried out in a uniform manner on the whole of the donor substrate to form therein an embrittlement plane which delimits the thin layer and a bulk part of the donor substrate, of placing in contact the donor substrate and the receiver substrate and of initiating and propagating a fracture wave along the embrittlement plane. The method comprises, before the placing in contact, a step of localised reduction of a capacity of the embrittlement plane to initiate the fracture wave. This step of localised reduction may be carried out by means of a localised laser annealing of the donor substrate.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: September 26, 2023
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Shay Reboh, Frédéric Mazen, Pablo Acosta Alba
  • Patent number: 11688629
    Abstract: A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650° C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: June 27, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Jean-Michel Hartmann
  • Patent number: 11670540
    Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 6, 2023
    Assignees: Soitec, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frédéric Mazen, Damien Massy, Shay Reboh, François Rieutord
  • Patent number: 11646196
    Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: May 9, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Heimanu Niebojewski, Christophe Plantier, Shay Reboh
  • Patent number: 11610806
    Abstract: A production method for a semi-conductor-on-insulator type multilayer stack includes ion implantation in a buried portion of a superficial layer of a support substrate, so as to form a layer enriched with at least one gas, intended to form a porous semi-conductive material layer, the thermal oxidation of a superficial portion of the superficial layer to form an oxide layer extending from the surface of the support substrate, the oxidation and the implantation of ions being arranged such that the oxide layer and the enriched layer are juxtaposed, and the assembly of the support substrate and of a donor substrate.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 21, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Pablo Acosta Alba