Patents by Inventor Shay REBOH

Shay REBOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508613
    Abstract: The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 22, 2022
    Assignee: COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pablo Acosta Alba, Shay Reboh
  • Patent number: 11469137
    Abstract: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 11, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Pablo Acosta Alba, Emmanuel Augendre
  • Patent number: 11450755
    Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 20, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20220293414
    Abstract: A method for modifying a strain state of at least one semiconductor layer includes providing a support over which is arranged at least one stack of layers including the semiconductor layer and a fusible layer, arranged between the semiconductor layer and the support. The method also includes melting at least one portion of the fusible layer the passage of said at least one portion of the fusible layer from a solid state into a liquid state, the semiconductor layer remaining in the solid state during the melting step. A laser beam may be used for the melting. The melting with the laser beam may also cause the modification of the strain state of the semiconductor layer.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 15, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Pablo ACOSTA ALBA
  • Publication number: 20220223467
    Abstract: A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 14, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Vincent LARREY, Frank FOURNEL
  • Publication number: 20220189994
    Abstract: Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 16, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland
  • Publication number: 20220172984
    Abstract: A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650° C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Jean-Michel Hartmann
  • Publication number: 20220157608
    Abstract: A method for forming a doped zone of a transistor includes providing a stack having at least one active layer made from a semiconductor material, and a transistor gate pattern having at least one lateral side, and modifying a portion of the active layer so as to form a modified portion made of a modified semiconductor material. The modified portion extends down to the at least one lateral side of the gate pattern, at the edge of a non-modified portion above which the gate pattern is located. The method also includes forming a spacer on the lateral side, removing the modified portion by selective etching of the modified semiconductor material with respect to the semiconductor material of the non-modified portion, so as to expose an edge of the non-modified portion, and forming the doped zone by epitaxy starting from the exposed edge.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 19, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay REBOH
  • Publication number: 20220157970
    Abstract: A method for forming at least one doped region of a transistor includes providing a stack having an insulating layer, an active layer, and a gate pattern having a first lateral flank and removing a first portion of the active layer not overlaid by the gate pattern and extending down to the gate pattern, at the edge of a second portion of the active layer overlaid by the gate pattern, so as to expose an edge of the second portion. The edge extends substantially in a continuation of the lateral flank of the gate pattern. The method also includes forming a first spacer having an L shape and having a basal portion in contact with the insulating layer and a lateral portion in contact with the lateral flank; forming a second spacer on the first spacer; removing the basal portion of the first spacer by selective etching with respect to the second spacer, so as to expose the edge of the second portion; and forming the doped region by epitaxy from the exposed edge.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 19, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay Reboh
  • Publication number: 20220157612
    Abstract: A method of polishing a semiconductor substrate, including: a) a step of multiple implantations of ions from an upper surface of the substrate, to modify the material of an upper portion of the substrate, the multiple implantation step comprising a plurality of successive implantations under different respective implantation orientations; and b) a step of selective removal of the upper portion of the substrate.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 19, 2022
    Applicant: Commissariat à I'Ènergie Atomique et aux Ènergies Alternatives
    Inventors: Shay Reboh, Jean-Michel Hartmann, Frederic Mazen, Frédéric Milesi
  • Publication number: 20220077310
    Abstract: A method for forming a source/drain region of a transistor includes providing a substrate carrying a transistor pattern, comprising a base portion having an upper face elongated along an axis, a channel surmounting the base portion, and a spacer transversely surrounding a lateral portion of the channel, forming a protective layer on a facet of the channel, so as to prevent an oxidation of the lateral portion of the channel, forming an additional insulation portion in the base portion, by oxidation from the upper face, removing the protective layer so as to expose the facet, and forming by lateral epitaxy, the source/drain region from said facet.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 10, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Jean-Pierre COLINGE
  • Publication number: 20220068638
    Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 3, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Heimanu NIEBOJEWSKI, Christophe PLANTIER, Shay REBOH
  • Patent number: 11217446
    Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 4, 2022
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Posseme, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
  • Patent number: 11177371
    Abstract: A method is provided for fabricating a double gate structure for transistors with superposed bars, including: providing, on a support, a stack including an alternation of one or several first bars based on a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Shay Reboh
  • Publication number: 20210328014
    Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay REBOH, Remi COQUAND, Nicolas LOUBET, Tenko YAMASHITA, Jingyun ZHANG
  • Publication number: 20210305097
    Abstract: The invention relates to a method for creating a substrate of the type semiconductor on insulator, comprising the following steps: a) providing a donor substrate comprising a monocrystalline support substrate, a smoothing layer and a semiconductor layer, the smoothing layer forming an etch stop layer with respect to the material of the support substrate; a?) implantation of ion species through the semiconductor layer so as to form a fragilization plane; b) creating an assembly by placing the donor substrate and a receiver substrate in contact; c) transferring the semiconductor layer and at least a part of the smoothing layer by detachment along the fragilization plane: wherein the semiconductor layer of the donor substrate provided in step a) is monocrystalline and in that it further comprises the following steps: before step b), amorphization of at least a part of the semiconductor layer to form an amorphous layer; during or after step c), recrystallization in solid phase of the amorphous layer to form a
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay REBOH
  • Patent number: 11121231
    Abstract: A method for fabricating a field-effect transistor includes: providing a structure including a first layer of semiconductor material, a doped second layer of semiconductor material arranged on top of the first layer of semiconductor material, the composition of which is different from that of the first layer, two spacers made of dielectric material arranged on top of the second layer of semiconductor material and separated by a groove, the second layer of semiconductor material being accessible at the bottom of the groove; etching the second layer of semiconductor material at the bottom of the groove until reaching the first layer of semiconductor material in such a way as to retain the second layer of semiconductor material beneath the spacers on either side of the groove; and then forming a gate stack in the groove.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 14, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Shay Reboh
  • Publication number: 20210257450
    Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 19, 2021
    Inventors: Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh
  • Patent number: 11088247
    Abstract: A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 10, 2021
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Kangguo Cheng, Remi Coquand, Nicolas Loubet
  • Patent number: 11081547
    Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 3, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang