Abstract: A method for forming a semiconductor device includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. A thickness of the first portion of the dielectric layer is adjusted by either reducing the thickness or depositing additional dielectric material. A capacitor top plate is formed over the first portion of the dielectric layer.

Abstract: A method for forming a semiconductor device includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. A thickness of the first portion of the dielectric layer is adjusted by either reducing the thickness or depositing additional dielectric material. A capacitor top plate is formed over the first portion of the dielectric layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A method for fabricating a pair of patterned target layers within a microelectronic product employs a pair of patterned etch mask layers of different thicknesses. The pair of patterned etch mask layers of different thicknesses provides that the pair of patterned target layers may be formed with individual linewidth control, absent fabrication or modification of a photomask to realize the same result. The method is particularly useful for fabricating pair of gate electrodes for use within CMOS devices.

Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

Abstract: A method is disclosed for improving the bonding strength of wire bonds on semiconductor chips. Aluminum-silicon-copper is employed as the metal for wire bonding-pads. Openings are formed in the passivation layer over the bonding-pads. The exposed metal in the openings is treated with a fluorine containing F-plasma. A thin passivation film, with C, F, and O content is formed over the metal bonding pads. This protective film prevents the formation of pitting and staining of the bonding-pads when the wafer is subjected to repeated developing solutions during the color filter process performed for the CMOS image sensors, for example. Consequently, the wire bonds formed during the packaging of the chips are stronger and more reliable.

Abstract: The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.

Abstract: An improved method for grinding a semiconductor chip to prepare it for scanning with SEM to view a defect includes the step of forming an electrically conductive coating on the top surface of the chip. The coating is made under a mask that produces a U shaped conductive pattern so that an electrical path is formed on the top surface of the chip between two corners of the pattern. An initial resistance measurement is made for this path and a known amount of the chip below the U shape is ground away and a second resistance measurement is made. From these measurements, a calculation is made that gives the resistance when the chip has been ground to a selected section line. The grinding operation then proceeds until this resistance is reached, and the usual practice of visually checking the chip during the grinding operation is avoided. The mask creates a point at the bottom of the U shape that points to the defect.