Patents by Inventor Shelby Ferguson

Shelby Ferguson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395460
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for supports for internal hardware of electronic devices. An example support includes an integrated circuit (IC) carrier that includes a plurality of walls, supports carried by the walls to support an IC from below the IC, and a retention clip to secure the IC.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 7, 2023
    Inventors: David Shia, Rick Canham, Eric W. Buddrius, Jeffory L. Smalley, John Beatty, Kenan Arik, Mohanraj Prabhugoud, Kirk Wheeler, Shelby Ferguson, Jorge Contreras Perez, Daniel Neumann, Ernesto Borboa Lizarraga
  • Publication number: 20230019643
    Abstract: Example integrated separator devices for hardware component separation are disclosed herein. An example apparatus include a processor carrier having an inner edge and an outer edge; and a component separator rotatably coupled to the processor carrier, the component separator including a shaft, an entirety of the component separator closer to a center of the processor carrier than the outer edge is to the center of the processor carrier.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Inventors: Daniel Neumann, Andrew Larson, Eric Buddrius, Jeffory Smalley, Shelby Ferguson
  • Patent number: 11296009
    Abstract: A microprocessor carrier comprising a lever having an elongate arm and a wedge structure extending from one end of the elongate arm, and a frame comprising and a fulcrum structure to receive the lever and a microprocessor. The fulcrum structure is to couple the lever to the frame.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Rolf Laido, Divya Swamy Bandaru, Thomas Boyd, Jorge Contreras Perez, Shelby A. Ferguson, Mustafa Haswarey
  • Patent number: 11291115
    Abstract: A microprocessor carrier, comprising a frame comprising a metal. The first frame surrounds an aperture for receiving a microprocessor package. At least one hinge assembly is on a first frame edge, and at least one latch assembly is on a second frame edge. One or more alignment tabs coupled to the frame. The one or more alignment tabs extend orthogonally from at least one frame edge. The alignment tabs are to align the microprocessor package with a microprocessor socket. The hinge assembly and the latch assembly are to engage with a microprocessor loading mechanism coupled to a printed circuit board.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Shelby A. Ferguson, Bijoyraj Sahu, Russell Aoki, Thomas Boyd, Eric W. Buddrius, Kevin Ceurter, Mustafa Haswarey, Rolf Laido, Daniel Neumann, Rachel Taylor, Anthony Valpiani
  • Patent number: 10455685
    Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Kuang Liu, Thomas A. Boyd, Luis Gil Rangel, Muffadal Mukadem, Shelby A. Ferguson, Francis Toth, Jr., Eric Buddrius, Ralph V. Miele, Sriram Srinivasan, Jeffory L. Smalley
  • Publication number: 20190304871
    Abstract: A microprocessor carrier comprising a lever having an elongate arm and a wedge structure extending from one end of the elongate arm, and a frame comprising and a fulcrum structure to receive the lever and a microprocessor. The fulcrum structure is to couple the lever to the frame.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Rolf Laido, Divya Swamy Bandaru, Thomas Boyd, Jorge Contreras Perez, Shelby A. Ferguson, Mustafa Haswarey
  • Publication number: 20190306985
    Abstract: A microprocessor carrier, comprising a frame comprising a metal. The first frame surrounds an aperture for receiving a microprocessor package. At least one hinge assembly is on a first frame edge, and at least one latch assembly is on a second frame edge. One or more alignment tabs coupled to the frame. The one or more alignment tabs extend orthogonally from at least one frame edge. The alignment tabs are to align the microprocessor package with a microprocessor socket. The hinge assembly and the latch assembly are to engage with a microprocessor loading mechanism coupled to a printed circuit board.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Shelby A. Ferguson, Bijoyraj Sahu, Russell Aoki, Thomas Boyd, Eric W. Buddrius, Kevin Ceurter, Mustafa Haswarey, Rolf Laido, Daniel Neumann, Rachel Taylor, Anthony Valpiani
  • Patent number: 10260961
    Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Shelby Ferguson, Rashelle Yee, Russell S. Aoki, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski
  • Patent number: 10178763
    Abstract: Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Rashelle Yee, Russell S. Aoki, Shelby Ferguson, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski, Kevin J. Ceurter
  • Publication number: 20180174940
    Abstract: Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Applicant: Intel Corporation
    Inventors: Shelby Ferguson, Gong Ouyang, Russell S. Aoki, Zhichao Zhang, Kai Xiao
  • Patent number: 9991223
    Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Michael R. Hui, Jonathon R. Carstens, Michael S. Brazel, Daniel P. Carter, Thomas A. Boyd, Shelby A. Ferguson, Rashelle Yee, Joseph J. Jasniewski, Harvey R. Kofstad, Anthony P. Valpiani
  • Publication number: 20170179066
    Abstract: Reflow Grid Array technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a BGA package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is solder cleaning and removal when removing a BGA package. Technical solutions described herein provide processes and equipment for bulk solder removal from a BGA package that can be executed in the field.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Russell S. Aoki, John W. Jaeger, Michael S. Brazel, Daniel P. Carter, Anthony P. Valpiani, Michael R. Hui, Rashelle Yee, Joseph J. Jasniewski, Shelby A. Ferguson, Thomas A. Boyd, Jonathan W. Thibado, Penny K. Woodcock, Rachel G. Taylor, Laura S. Mortimer
  • Publication number: 20170179067
    Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: RUSSELL S. AOKI, MICHAEL R. HUI, JONATHON R. CARSTENS, MICHAEL S. BRAZEL, DANIEL P. CARTER, THOMAS A. BOYD, SHELBY A. FERGUSON, RASHELLE YEE, JOSEPH J. JASNIEWSKI, HARVEY R. KOFSTAD, ANTHONY P. VALPIANI
  • Publication number: 20170178994
    Abstract: Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled to the first heater trace in the IC package support structure.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Michael Hui, Rashelle Yee, Jonathan Thibado, Daniel P. Carter, Shelby Ferguson, Anthony P. Valpiani, Russell S. Aoki, Jonathon Robert Carstens, Joseph J. Jasniewski, Harvey R. Kofstad, Michael Brazel, Tracy Clack, Viktor Vogman, Penny Woodcock, Kevin J. Ceurter, Hongfei Yan
  • Publication number: 20170181271
    Abstract: Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Rashelle Yee, Russell S. Aoki, Shelby Ferguson, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski, Kevin J. Ceurter
  • Publication number: 20170176260
    Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Shelby Ferguson, Rashelle Yee, Russell S. Aoki, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski