Patents by Inventor Sheng-Chau Chen
Sheng-Chau Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352516Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.Type: ApplicationFiled: July 4, 2023Publication date: November 2, 2023Inventors: SHENG-CHAU CHEN, CHENG-HSIEN CHOU, MIN-FENG KAO
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Patent number: 11804473Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.Type: GrantFiled: May 28, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Publication number: 20230343817Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Inventors: Alexander Kalnitsky, Ru-Liang Lee, Ming Chyi Liu, Sheng-Chan Li, Sheng-Chau Chen
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Publication number: 20230317541Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
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Publication number: 20230290672Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Tzu-Jui Wang, Sheng-Chan Li
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Publication number: 20230275064Abstract: Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20230268367Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
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Patent number: 11735617Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.Type: GrantFiled: April 21, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Min-Feng Kao
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Patent number: 11735624Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.Type: GrantFiled: June 29, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Ru-Liang Lee, Ming Chyi Liu, Sheng-Chan Li, Sheng-Chau Chen
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Patent number: 11715674Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.Type: GrantFiled: October 14, 2021Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
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Patent number: 11705360Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.Type: GrantFiled: March 10, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Tzu-Jui Wang, Sheng-Chan Li
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Publication number: 20230207448Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.Type: ApplicationFiled: February 13, 2023Publication date: June 29, 2023Inventors: Paul YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
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Patent number: 11682652Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.Type: GrantFiled: March 10, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20230187294Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.Type: ApplicationFiled: March 21, 2022Publication date: June 15, 2023Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo, Ping-Tzu Chen, Cheng-Yuan Tsai
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Patent number: 11670539Abstract: A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.Type: GrantFiled: February 22, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
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Patent number: 11664411Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.Type: GrantFiled: April 22, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Che Lee, Sheng-Chau Chen, I-Nan Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
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Publication number: 20230154898Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Inventors: Kuo-Ming Wu, Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou
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Patent number: 11652124Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.Type: GrantFiled: October 14, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Wei Huang, Chao-Ching Chang, Yun-Wei Cheng, Chih-Lung Cheng, Yen-Chang Chen, Wen-Jen Tsai, Cheng Han Lin, Yu-Hsun Chih, Sheng-Chan Li, Sheng-Chau Chen
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Publication number: 20230129760Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
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Publication number: 20230103309Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang