Patents by Inventor Sheng-Chin Kung

Sheng-Chin Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411656
    Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
  • Patent number: 10861722
    Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 8, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Benjamin Colombeau, Sheng-Chin Kung, Patricia M. Liu
  • Patent number: 10777650
    Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
  • Publication number: 20200152493
    Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 14, 2020
    Inventors: Benjamin COLOMBEAU, Sheng-Chin KUNG, Patricia M. LIU
  • Publication number: 20200144397
    Abstract: Methods and apparatuses for processing substrates, such as during silicon-germanium pre-cleans, are provided. A method includes introducing the substrate into a processing system, where the substrate contains a plurality of silicon-containing (e.g., SiGe) fins and a contaminant disposed on the silicon-containing fins, and exposing the substrate to a plasma treatment to remove at least a portion of the contaminant disposed from the silicon-containing fins. The method also includes exposing the substrate to an oxidation treatment to produce an oxide layer on the silicon-containing fins and the remaining contaminant thereon, then exposing the substrate to a dry-clean treatment to remove the oxide layer and the remaining contaminant from the silicon-containing fins and produce a cleaned surface thereon, and depositing an epitaxial layer on the cleaned surface on the silicon-containing fins.
    Type: Application
    Filed: September 17, 2019
    Publication date: May 7, 2020
    Applicants: Applied Materials, Inc., Applied Materials, Inc.
    Inventors: Abhishek DUBE, Sheng-Chin KUNG, Malcolm BEVAN, Johanes SWENBERG
  • Patent number: 10249479
    Abstract: Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 2, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Joseph F. Aubuchon, Tza-Jing Gung, Travis Lee Koh, Nattaworn Boss Nunta, Sheng-Chin Kung, Steven Lane, Kartik Ramaswamy, Yang Yang
  • Publication number: 20180166570
    Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 14, 2018
    Inventors: Sheng-Chin KUNG, Hua CHUNG
  • Patent number: 9966438
    Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 8, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Hua Chung, Sheng-Chin Kung, Xuebin Li
  • Publication number: 20180083104
    Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.
    Type: Application
    Filed: January 27, 2017
    Publication date: March 22, 2018
    Inventors: Yi-Chiau HUANG, Hua CHUNG, Sheng-Chin KUNG, Xuebin LI
  • Publication number: 20170309719
    Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 26, 2017
    Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
  • Publication number: 20160225590
    Abstract: Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.
    Type: Application
    Filed: December 31, 2015
    Publication date: August 4, 2016
    Inventors: Joseph F. Aubuchon, Tza-Jing Gung, Travis Lee Koh, Nattaworn Nuntaworanuch, Sheng-Chin Kung, Steven Lane, Kartik Ramaswamy, Yang Yang
  • Publication number: 20040109813
    Abstract: An art is provided to realize a current emitting device capable of emitting current of higher density under the same or lower onset emission voltage. The current emitting device is preferably an array of carbon nanotubes or a film including carbon nanotubes. The art is based on oxidizing a current emitting device composed of material including carbon, until the current emitting device has at least part thereof changed in shape. The current emitting device thus processed works better with a display, or becomes capable of emitting current of higher density under the same or lower onset emission voltage. As far as experiments showed, the emitted current density achieved by the art can be eight times the amount emitted by an array of nanotubes having not been processed according to the art, and the onset emission voltage can be lowered by the art from 0.8 V/&mgr;m to 0.5 V/&mgr;m.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Applicant: National Tsing Hua University
    Inventors: Kuo-Chu Hwang, Sheng-Chin Kung