Patents by Inventor Shenghong Wang
Shenghong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240084979Abstract: A light bulb apparatus includes a glass housing, a sleeve housing, a light source plate, a sleeve connector wrapping and an Edison cap. The glass housing defines a tubular part and a trumpet part. The sleeve housing includes a neck part and a protruding part. The neck part is enclosed by the tubular part of the glass housing. The protruding part is exposed outside tubular part. The light source plate is fixed to the sleeve housing. The sleeve connector wraps an exterior surface of the protruding part. The Edison cap is attached to the sleeve connector.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: Mingnan Su, Guangai Chen, Chunhua Wang, Shenghong Liu
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Patent number: 9766895Abstract: A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.Type: GrantFiled: November 12, 2014Date of Patent: September 19, 2017Assignee: Optimum Semiconductor Technologies, Inc.Inventors: Shenghong Wang, C. John Glossner, Gary J. Nacer
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Patent number: 9766894Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.Type: GrantFiled: November 12, 2014Date of Patent: September 19, 2017Assignee: Optimum Semiconductor Technologies, Inc.Inventors: C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur J. Hoane, Paul D'Arcy, Sabin D. Iancu, Shenghong Wang
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Patent number: 9740498Abstract: Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a third clock period are respectively allocated to the zeroth thread, the first thread, the second thread and the third thread; if one of the threads cannot issue an instruction within a specified clock period because the instruction is not ready, and the previous thread still has an instruction ready to be executed after issuing certain instructions in the previous specified clock period, then the previous thread will take the specified clock period.Type: GrantFiled: November 15, 2012Date of Patent: August 22, 2017Assignee: Wuxi DSP Technologies Inc.Inventor: Shenghong Wang
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Patent number: 9558000Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.Type: GrantFiled: November 12, 2014Date of Patent: January 31, 2017Assignee: Optimum Semiconductor Technologies, Inc.Inventors: C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur J. Hoane, Paul D'Arcy, Sabin D. Iancu, Shenghong Wang
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Publication number: 20150220347Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.Type: ApplicationFiled: November 12, 2014Publication date: August 6, 2015Inventors: C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur J. Hoane, Paul D'Arcy, Sabin D. Iancu, Shenghong Wang
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Publication number: 20150220342Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.Type: ApplicationFiled: November 12, 2014Publication date: August 6, 2015Inventors: C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur J. Hoane, Paul D'Arcy, Sabin D. Iancu, Shenghong Wang
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Publication number: 20150220346Abstract: A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.Type: ApplicationFiled: November 12, 2014Publication date: August 6, 2015Inventors: Shenghong Wang, C. John Glossner, Gary J. Nacer
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Publication number: 20140351568Abstract: Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a third clock period are respectively allocated to the zeroth thread, the first thread, the second thread and the third thread; if one of the threads cannot issue an instruction within a specified clock period because the instruction is not ready, and the previous thread still has an instruction ready to be executed after issuing certain instructions in the previous specified clock period, then the previous thread will take the specified clock period.Type: ApplicationFiled: November 15, 2012Publication date: November 27, 2014Inventor: Shenghong Wang
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Patent number: 8732382Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.Type: GrantFiled: August 5, 2009Date of Patent: May 20, 2014Assignee: QUALCOMM IncorporatedInventors: Mayan Moudgill, Shenghong Wang
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Patent number: 8471597Abstract: A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.Type: GrantFiled: May 7, 2009Date of Patent: June 25, 2013Assignee: Qualcomm IncorporatedInventors: Shenghong Wang, Mayan Moudgill, Gary Nacer
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Publication number: 20110254588Abstract: A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.Type: ApplicationFiled: May 7, 2009Publication date: October 20, 2011Applicant: ASPEN ACQUISITION CORPORATIONInventors: Gary Nacer, Mayan Moudgill, Shenghong Wang
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Publication number: 20110252211Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.Type: ApplicationFiled: August 5, 2009Publication date: October 13, 2011Applicant: Aspen Acquisition CorporationInventors: Mayan Moudgill, Shenghong Wang
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Publication number: 20110241744Abstract: A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.Type: ApplicationFiled: August 20, 2009Publication date: October 6, 2011Applicant: Aspen Acquisition CorporationInventors: Mayan Moudgill, Gary Nacer, Shenghong Wang
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Patent number: 6990557Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.Type: GrantFiled: June 4, 2002Date of Patent: January 24, 2006Assignee: Sandbridge Technologies, Inc.Inventors: Erdem Hokenek, C. John Glossner, Arthur Joseph Hoane, Mayan Moudgill, Shenghong Wang
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Patent number: 6912623Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.Type: GrantFiled: June 4, 2002Date of Patent: June 28, 2005Assignee: Sandbridge Technologies, Inc.Inventors: Erdem Hokenek, C. John Glossner, Arthur Joseph Hoane, Mayan Moudgill, Shenghong Wang
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Patent number: 6845274Abstract: An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permitting the microprocessor at the lighting device to incur substantially less processing load.Type: GrantFiled: January 24, 2001Date of Patent: January 18, 2005Assignee: Koninklijke Philips Electronics N.V.Inventor: Shenghong Wang
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Patent number: 6710993Abstract: A method and apparatus for voltage/current overage condition protection for a lighting control circuit. The method provides a hybrid software and hardware solution to take advantage of the useful attributes of both. Overages are sensed in hardware by digital comparators, where the thresholds used as the basis for comparison are predefined in software. When an overage is detected, the circuit outputs, which are controlled by a plurality of counters, are changed by changing the source of the pulse width data used by the counters from software control to predetermined minima stored in a plurality of registers.Type: GrantFiled: November 27, 2000Date of Patent: March 23, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Shenghong Wang
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Publication number: 20030225976Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.Type: ApplicationFiled: June 4, 2002Publication date: December 4, 2003Inventors: Erdem Hokenek, C. John Glossner, Arthur Joseph Hoane, Mayan Moudgill, Shenghong Wang
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Publication number: 20030225975Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.Type: ApplicationFiled: June 4, 2002Publication date: December 4, 2003Inventors: Erdem Hokenek, C. John Glossner, Arthur Joseph Hoane, Mayan Moudgill, Shenghong Wang