Abstract: An additive manufacturing apparatus includes a platform, a dispenser configured to deliver a plurality of successive layers of feed material onto the platform, at least one light source configured to generate a first light beam and a second light beam, a polygon mirror scanner, an actuator, and a galvo mirror scanner. The polygon mirror scanner is configured to receive the first light beam and reflect the first light beam towards the platform. Rotation of the first polygon mirror causes the light beam to move in a first direction along a path on a layer of feed material on the platform. The actuator is configured to cause the path to move along a second direction at a non-zero angle relative to the first direction. The galvo mirror scanner system is configured to receive the second light beam and reflect the second light beam toward the platform.

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

Abstract: Embodiments of the present disclosure relate to methods for dicing one or more optical devices from a substrate with a laser machining system. The laser machining system utilizes a laser to perform methods for dicing one or more optical devices from a substrate along a dicing path. The methods use one of forming a plurality of laser spots along the dicing path or forming a plurality of trenches along the dicing path.

Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

Abstract: Exemplary processing methods may include translating a lithium film beneath a first showerhead. The methods may include introducing an oxidizer gas through the first showerhead onto the lithium film. The methods may include forming an oxide monolayer on the lithium film. The oxide monolayer may be or include the oxidizer gas adsorbed on the lithium film. The methods may include translating the lithium film beneath a second showerhead after forming the oxide monolayer. The methods may include introducing a carbon source gas through the first showerhead onto the lithium film. The methods may also include converting the oxide monolayer into a carbonate passivation layer through reaction of the oxide monolayer with the carbon source gas.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, a breakthrough treatment is performed, the breakthrough treatment comprising a first physical bombardment operation, a second iterative isotropic and directional plasma etch operation, and a third directional breakthrough operation. Subsequent to performing the breakthrough treatment, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A foundry dust compound reinforcing filler for natural rubber contains 40-80 parts by weight of foundry dust, 10-40 parts by weight of silica and 10-40 parts by weight of Carbon black. A method for preparing a foundry dust compound reinforcing filler for natural rubber includes the steps of sieving, iron removal, pickling, precipitation, primary grinding, mixing, secondary grinding, granulation and the like. The foundry dust compound reinforcing filler used for reinforcing natural rubber is easy to disperse in natural rubber. The compound reinforcing filler has excellent reinforcing effect, which realizes the resource utilization of casting dust waste and reduces the consumption of silica and carbon black.

Abstract: A foundry dust compound reinforcing filler for natural rubber contains 40-80 parts by weight of foundry dust, 10-40 parts by weight of silica and 10-40 parts by weight of Carbon black. A method for preparing a foundry dust compound reinforcing filler for natural rubber includes the steps of sieving, iron removal, pickling, precipitation, primary grinding, mixing, secondary grinding, granulation and the like. The foundry dust compound reinforcing filler used for reinforcing natural rubber is easy to disperse in natural rubber. The compound reinforcing filler has excellent reinforcing effect, which realizes the resource utilization of casting dust waste and reduces the consumption of silica and carbon black.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: In an embodiment, a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer is provided. The method includes detecting the mask layer by a sensor, the mask layer providing a substrate surface; determining a property of the blind via, the property comprising one or more of a top diameter, a bottom diameter, a volume, or a taper angle; focusing a Gaussian laser beam, under laser process parameters, at the substrate surface to remove at least a portion of the mask layer; adjusting the laser process parameters based on the property; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. The mask layer can be pre-etched. Apparatus for forming a blind via in a substrate are also provided.

Abstract: Embodiments of the present disclosure provide a BWP allocation method, apparatus, electronic device, and a computer-readable storage medium, and relate to the field of communication technologies. The method includes: acquiring service-related information of at least one base station; determining configuration information of the bandwidth part (BWP) of the at least one base station based on the service-related information of the at least one base station; and configuring the BWP of the at least one base station based on the configuration information. The BWP allocation method may meet requirements of different services and different user capabilities, improve a network throughput, and reduce energy consumption.

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.

Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

Abstract: A (Z)-solanone has the steric formula of: or with the name of (S,Z)-5-isopropyl-8-methyl-6,8-diene-2-one or (R,Z)-5-isopropyl-8-methyl-6,8-diene-2-one. A process for the preparation of the (Z)-type solanone and the use thereof in flavoring of cigarette shred are further disclosed. The process includes the following steps: (1) reacting isopentanal and methyl vinyl ketone, under the action of a catalyst and a co-catalyst, to give (S)-2-isopropyl-5-carbonylhexanal or (R)-2-isopropyl-5-carbonylhexanal; (2) reacting the (S)-2-isopropyl-5-carbonylhexanal or the (R)-2-isopropyl-5-carbonylhexanal obtained in step (1) with (iodomethyl)triphenylphosphonium iodide, to give (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or (R,Z)-7-iodo-5-isopropyl-6-ene-2-one; and (3) reacting the (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or the (R,Z)-7-iodo-5-isopropyl-6-ene-2-one obtained in step (2) with pinacol isopropenylborate in the presence of a catalyst to give the (Z)-solanone.

Abstract: A (Z)-solanone has the steric formula of: with the name of (S,Z)-5-isopropyl-8-methyl-6,8-diene-2-one or (R,Z)-5-isopropyl-8-methyl-6,8-diene-2-one. A process for the preparation of the (Z)-type solanone and the use thereof in flavoring of cigarette shred are further disclosed. The process includes the following steps: (1) reacting isopentanal and methyl vinyl ketone, under the action of a catalyst and a co-catalyst, to give (S)-2-isopropyl-5-carbonylhexanal or (R)-2-isopropyl-5-carbonylhexanal; (2) reacting the (S)-2-isopropyl-5-carbonylhexanal or the (R)-2-isopropyl-5-carbonylhexanal obtained in step (1) with (iodomethyl)triphenylphosphonium iodide, to give (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or (R,Z)-7-iodo-5-isopropyl-6-ene-2-one; and (3) reacting the (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or the (R,Z)-7-iodo-5-isopropyl-6-ene-2-one obtained in step (2) with pinacol isopropenylborate in the presence of a catalyst to give the (Z)-solanone.

Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.