Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Abstract: Via chain and serpentine/comb test structures are in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area.

Abstract: A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.

Abstract: Via chain and serpentine/comb test structures are in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area.

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

Abstract: A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.