Patents by Inventor SHI YOU
SHI YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923244Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.Type: GrantFiled: March 5, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Shi You, Mehul B. Naik
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Publication number: 20240038541Abstract: Methods for cleaning oxides from a substrate surface are performed without affecting low-k dielectric or carbon materials on the substrate. In some embodiments, the method may include performing a preclean process with a chlorine-based soak to remove oxides from a surface of a substrate in a back end of the line (BEOL) process and treating the surface of the substrate with a remote plasma with a hydrogen gas and at least one inert gas to remove residual chlorine residue from the surface of the substrate without damaging low-k dielectric material or carbon material on the substrate.Type: ApplicationFiled: October 6, 2022Publication date: February 1, 2024Inventors: Jiajie CEN, Xiaodong WANG, Kevin KASHEFI, Shi YOU
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Patent number: 11791413Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.Type: GrantFiled: August 2, 2021Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
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Publication number: 20230187204Abstract: Provided are methods for pre-cleaning a substrate. A substrate having tungsten oxide (WOx) thereon is soaked in tungsten fluoride (WF6), which reduces the tungsten oxide (WOx) to tungsten (W). Subsequently, the substrate is treated with hydrogen, e.g., plasma treatment or thermal treatment, to reduce the amount of fluorine present so that fluorine does not invade the underlying insulating layer.Type: ApplicationFiled: June 20, 2022Publication date: June 15, 2023Applicant: Applied Materials, Inc.Inventors: Xiaodong Wang, Kevin Kashefi, Rongjun Wang, Shi You, Keith T. Wong, Yuchen Liu, Ya-Hsi Hwang, Jean Lu
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Publication number: 20230187276Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Inventors: Shi YOU, He REN, Naomi YOSHIDA, Nikolaos BEKIARIS, Mehul NAIK, Jay Martin SEAMONS, Jingmei LIANG, Mei-Yee SHEK
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Patent number: 11664425Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: GrantFiled: January 20, 2022Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11646349Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.Type: GrantFiled: October 27, 2021Date of Patent: May 9, 2023Assignee: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11615984Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: GrantFiled: April 14, 2020Date of Patent: March 28, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Shi You, He Ren, Naomi Yoshida, Nikolaos Bekiaris, Mehul Naik, Martin Jay Seamons, Jingmei Liang, Mei-Yee Shek
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Publication number: 20230014253Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.Type: ApplicationFiled: August 2, 2021Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
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Patent number: 11557654Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.Type: GrantFiled: October 27, 2021Date of Patent: January 17, 2023Assignee: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11515200Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.Type: GrantFiled: December 3, 2020Date of Patent: November 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Yi Xu, Yufei Hu, He Ren, Yu Lei, Shi You, Kazuya Daito
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Publication number: 20220285212Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: He REN, Hao JIANG, Shi YOU, Mehul B. NAIK
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Publication number: 20220181201Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Applied Materials, Inc.Inventors: Yi XU, Yufei HU, He REN, Yu LEI, Shi YOU, Kazuya DAITO
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Publication number: 20220157814Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.Type: ApplicationFiled: December 22, 2020Publication date: May 19, 2022Inventors: Shi-You Liu, Ming-Shiou Hsieh, Zih-Hsuan Huang, Tsai-Yu Wen, Yu-Ren Wang
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Publication number: 20220140080Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20220093742Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.Type: ApplicationFiled: October 27, 2021Publication date: March 24, 2022Applicant: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Publication number: 20220093741Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.Type: ApplicationFiled: October 27, 2021Publication date: March 24, 2022Applicant: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11271078Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: GrantFiled: April 1, 2020Date of Patent: March 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11195918Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.Type: GrantFiled: September 18, 2020Date of Patent: December 7, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11164780Abstract: Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.Type: GrantFiled: June 7, 2019Date of Patent: November 2, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Shi You, He Ren, Mehul Naik, Yi Xu, Feng Chen