Patents by Inventor Shiang-Bau Wang

Shiang-Bau Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707072
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed adjacent to the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the first fin structure is lower than the second fin structure, and the first fin structure has a curved top surface under the isolation structure.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shiang-Bau Wang
  • Publication number: 20200176318
    Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.
    Type: Application
    Filed: May 1, 2019
    Publication date: June 4, 2020
    Inventors: Shu-Uei Jang, Chen-Huang Huang, Ryan Chia-Jen Chen, Shiang-Bau Wang, Shu-Yuan Ku
  • Publication number: 20200126868
    Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
    Type: Application
    Filed: June 3, 2019
    Publication date: April 23, 2020
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Chen-Huang Huang, Ming-Jhe Sie, Ryan Chia-Jen Chen
  • Publication number: 20200119005
    Abstract: A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 16, 2020
    Inventor: Shiang-Bau WANG
  • Publication number: 20200105583
    Abstract: A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.
    Type: Application
    Filed: November 1, 2018
    Publication date: April 2, 2020
    Inventors: Shiang-Bau Wang, Chun-Hung Lee
  • Publication number: 20200044070
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 6, 2020
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
  • Publication number: 20200004134
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Patent number: 10504893
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate and an isolation structure formed on the substrate. The first fin structure is embedded in the isolation structure, and the first fin structure has an upper portion and a lower portion. The upper portion is above the isolation structure, and the lower portion is below the isolation structure. The FinFET device structure also includes a protection layer formed on the sidewalls of the lower portion of the first fin structure.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shiang-Bau Wang
  • Patent number: 10481483
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Publication number: 20190341470
    Abstract: A method of manufacturing a semiconductor device includes: forming a gate over a semiconductor substrate; forming doped regions in the semiconductor substrate on both sides of the gate; depositing a dielectric layer on sidewalls of the gate; depositing a spacer laterally surrounding the dielectric layer, the spacer including a carbon-free portion and a carbon-containing portion laterally surrounding the carbon-free portion; removing the gate and vertical portions of the dielectric layer to form a recess; and filling a conductive layer in the recess.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventor: SHIANG-BAU WANG
  • Publication number: 20190259140
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Patent number: 10355131
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate comprising two source/drain regions, a gate stack over the semiconductor substrate and between the source/drain regions, and a spacer over the semiconductor substrate and surrounding the gate stack. The spacer comprises a carbon-containing layer and a carbon-free layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shiang-Bau Wang
  • Patent number: 10304178
    Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY, LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Publication number: 20190131122
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed adjacent to the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the first fin structure is lower than the second fin structure, and the first fin structure has a curved top surface under the isolation structure.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 2, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shiang-Bau WANG
  • Patent number: 10269787
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Ming-Ching Chang, Shu-Yuan Ku, Ryan Chia-Jen Chen
  • Publication number: 20190109126
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Application
    Filed: November 29, 2018
    Publication date: April 11, 2019
    Inventors: Shiang-Bau Wang, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ming-Ching Chang
  • Publication number: 20190006345
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Application
    Filed: November 10, 2017
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: SHIANG-BAU WANG, MING-CHING CHANG, SHU-YUAN KU, RYAN CHIA-JEN CHEN
  • Publication number: 20190004416
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: January 3, 2019
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Patent number: 10163624
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. The semiconductor structure further includes the first fin structure has a first height and the second fin structure has a second height higher than the first height, and the gate structure and the first fin structure are separated by the isolation structure.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shiang-Bau Wang
  • Patent number: 10020198
    Abstract: The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes forming a polysilicon stripe over a semiconductor fin, forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe, forming a raised source/drain region in the semiconductor fin, and forming a carbonitride etch stop layer surrounding the nitride sidewall spacer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shiang-Bau Wang, Victor Y. Lu