Patents by Inventor Shiang Yang Ong

Shiang Yang Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7767577
    Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: August 3, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
  • Patent number: 7727856
    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.
    Type: Grant
    Filed: December 24, 2006
    Date of Patent: June 1, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
  • Publication number: 20090206408
    Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 20, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
  • Publication number: 20090090975
    Abstract: An integrated circuit system that includes: providing a substrate including a first integrated circuit region electrically connected to a second integrated circuit region; implanting a dielectric growth material underneath a gate for each of an NFET device and a PFET device within the first integrated circuit region and the second integrated circuit region; and annealing the integrated circuit system.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shiang Yang Ong, Shyue Seng Tan, Xiangdong Chen, Jae Gon Lee, Lee Wee Teo
  • Patent number: 7400018
    Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: July 15, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chung Foong Tan, Jinping Liu, Hyeok Jae Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong
  • Publication number: 20080150037
    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.
    Type: Application
    Filed: December 24, 2006
    Publication date: June 26, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD
    Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
  • Publication number: 20060270168
    Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.
    Type: Application
    Filed: August 7, 2006
    Publication date: November 30, 2006
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Chung Foong Tan, Jinping Liu, Hyeok Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong
  • Patent number: 7109099
    Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: September 19, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chung Foong Tan, Jinping Liu, Hyeok Jae Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong