Patents by Inventor Shigeharu Matsushita

Shigeharu Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7933161
    Abstract: A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads data from and rewrites data in the memory cell in a power-down state.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 26, 2011
    Assignee: Patrenella Capital Ltd., LLC
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Patent number: 7652908
    Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: January 26, 2010
    Inventors: Hideaki Miyamoto, Naofumi Sakai, Kouichi Yamada, Shigeharu Matsushita
  • Patent number: 7440307
    Abstract: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshiki Murayama, Shigeharu Matsushita
  • Patent number: 7420833
    Abstract: A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: September 2, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toru Dan, Naofumi Sakai, Shigeharu Matsushita, Yoshiyuki Ishizuka
  • Patent number: 7379323
    Abstract: This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion exercising control for selecting a prescribed memory cell block from among the plurality of memory cell blocks on the basis of comparison data output from the comparator and preferentially rewriting data in the memory cells included in the selected memory cell block.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 27, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Patent number: 7366004
    Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: April 29, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideaki Miyamoto, Naofumi Sakai, Kouichi Yamada, Shigeharu Matsushita
  • Patent number: 7362642
    Abstract: A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS2 at least either before or after different internal access operations corresponding to different external access operations respectively.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: April 22, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Patent number: 7297559
    Abstract: A method of fabricating a memory capable of improving the strength of a signal read from a memory cell is provided. This method of fabricating a memory comprises steps of forming a storage part and an etched thin-film part by partially etching a storage material film formed on a first electrode film by a prescribed thickness, forming an insulator film to cover at least the thin-film part of the storage material film and patterning the insulator film and the thin-film part of the storage material film by forming an etching mask on a prescribed region of the insulator film and thereafter etching the insulator film and the thin-film part of the storage material film through the etching mask.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 20, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Publication number: 20070237016
    Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).
    Type: Application
    Filed: June 16, 2005
    Publication date: October 11, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hideaki Miyamoto, Naofumi Sakai, Kouichi Yamada, Shigeharu Matsushita
  • Patent number: 7247900
    Abstract: A dielectric device having excellent characteristics is provided. This dielectric device comprises such a first electrode layer that constituent elements located on its surface are terminated by halogen atoms and a dielectric film formed on the surface of the first electrode layer terminated by the halogen atoms. When the constituent elements for the first electrode layer located on the surface thereof are terminated by the halogen atoms in order to form a ferroelectric film having a bismuth layer structure, therefore, Bi constituting the ferroelectric film is inhibited from bonding to the constituent elements located on the surface of the first electrode layer.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 24, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Publication number: 20070121365
    Abstract: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.
    Type: Application
    Filed: October 23, 2006
    Publication date: May 31, 2007
    Inventors: Yoshiki Murayama, Shigeharu Matsushita
  • Publication number: 20070070764
    Abstract: This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion exercising control for selecting a prescribed memory cell block from among the plurality of memory cell blocks on the basis of comparison data output from the comparator and preferentially rewriting data in the memory cells included in the selected memory cell block.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 29, 2007
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Publication number: 20070064514
    Abstract: A control unit capable of reliably preventing loss of data also when losing power during data processing is obtained. This control unit comprises a volatile memory temporarily storing data used in the control unit and a nonvolatile memory holding data of the volatile memory, for writing the same data as that written in the volatile memory also in the nonvolatile memory upon occurrence of writing in the volatile memory.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 22, 2007
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita, Shinichiro Okada
  • Publication number: 20070047363
    Abstract: A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads and rewrites data from and in the memory cell in a power-down state.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Publication number: 20070025172
    Abstract: A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS2 at least either before or after different internal access operations corresponding to different external access operations respectively.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • Patent number: 7167386
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected cell by increasing the ratio between voltages applied to ferroelectric capacitors of a selected cell and the non-selected cell respectively is obtained. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a memory cell including a switching element arranged between the bit line and the word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions and a ferroelectric capacitor arranged between the bit line and the word line and serially connected to the switching element.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: January 23, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Publication number: 20060164877
    Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 27, 2006
    Inventors: Hideaki Miyamoto, Naofumi Sakai, Kouichi Yamada, Shigeharu Matsushita
  • Publication number: 20060063279
    Abstract: A method of fabricating a memory capable of improving the strength of a signal read from a memory cell is provided. This method of fabricating a memory comprises steps of forming a storage part and an etched thin-film part by partially etching a storage material film formed on a first electrode film by a prescribed thickness, forming an insulator film to cover at least the thin-film part of the storage material film and patterning the insulator film and the thin-film part of the storage material film by forming an etching mask on a prescribed region of the insulator film and thereafter etching the insulator film and the thin-film part of the storage material film through the etching mask.
    Type: Application
    Filed: October 28, 2005
    Publication date: March 23, 2006
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Patent number: 6977402
    Abstract: A memory includes a first electrode film, a storage material film formed on the first electrode film, provided with a storage part and a thin-film part having a thickness smaller than a thickness of the storage part and which is at least about 15% of the thickness of the storage part on average, a second electrode film formed on the storage part of the storage material film. The thickness of the thin-film part may be between 15% and 95% of the thickness of the storage part. An insulator film may be formed on the thin-film part and the second electrode part, the insulator film formed on the thin-film part having a same pattern as the thin-film part.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 20, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Patent number: 6930906
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: August 16, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Yoh Takano, Satoru Sekine