Abstract: A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack.

Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

Abstract: A method of making three-dimensional memory device includes forming a stack of insulating layers and silicon nitride sacrificial layers over a substrate, forming memory stack structures in the alternating stack, forming a trench through the alternating stack, selectively etching the silicon nitride sacrificial layers through the trench using a phosphoric acid solution, filling a sample container with a fixed quantity of the phosphoric acid solution that was used to etch the silicon nitride sacrificial layers, determining a weight of the sample container, determining if a threshold value indicative of the etching end point has been reached or exceeded based on the determined weight, stopping the etching of the silicon nitride sacrificial layers in response to determining that the threshold value indicative of the etching end point has been reached or exceeded to leave recesses between the insulating layers, and filling the recesses with electrically conductive layers.

Abstract: A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

Abstract: A method of making three-dimensional memory device includes forming a stack of insulating layers and silicon nitride sacrificial layers over a substrate, forming memory stack structures in the alternating stack, forming a trench through the alternating stack, selectively etching the silicon nitride sacrificial layers through the trench using a phosphoric acid solution, filling a sample container with a fixed quantity of the phosphoric acid solution that was used to etch the silicon nitride sacrificial layers, determining a weight of the sample container, determining if a threshold value indicative of the etching end point has been reached or exceeded based on the determined weight, stopping the etching of the silicon nitride sacrificial layers in response to determining that the threshold value indicative of the etching end point has been reached or exceeded to leave recesses between the insulating layers, and filling the recesses with electrically conductive layers.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.

Abstract: A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

Abstract: An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

Abstract: A liquid processing apparatus of the present disclosure performs a liquid processing by supplying a processing liquid to a substrate that is rotating. A substrate holding unit configured to be rotatable around a vertical axis is provided with a holding surface to attract and hold a bottom surface of the substrate horizontally. A guide unit is formed integrally with the substrate holding unit, disposed around the substrate held in the substrate holding unit, and provided at a position equal to or lower than a height of a top surface of a periphery of the substrate. The guide unit includes a guide surface configured to guide the processing liquid. A rotary cup rotates integrally with the substrate holding unit, and guides the processing liquid towards the cup between the rotary cup and the guide unit.

Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.