Patents by Inventor Shigeki Kobayashi

Shigeki Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10975187
    Abstract: To optimize the primary particle size of a modified PTFE fine powder to shorten the sintering time during the extrusion molding. A modified polytetrafluoroethylene fine powder which is a fine powder of a non-melt-processable modified polytetrafluoroethylene comprising units derived from tetrafluoroethylene, units derived from hexafluoropropylene, units derived from a perfluoro(alkyl vinyl ether) represented by CF2?CFO—CnF2n+1 (n is an integer of from 1 to 6) and units derived from a (perfluoalkyl)ethylene represented by CH2?CH—CmF2m+1 (m is an integer of from 3 to 7).
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 13, 2021
    Assignees: AGC Inc., AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki Kobayashi, Ariana Claudia Morgovan-Ene, Anthony Eugene Wade
  • Patent number: 10971515
    Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Masaru Kito, Yasuhiro Uchiyama
  • Publication number: 20210082947
    Abstract: A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.
    Type: Application
    Filed: February 25, 2020
    Publication date: March 18, 2021
    Inventors: Shigeki KOBAYASHI, Toru MATSUDA, Hanae ISHIHARA
  • Patent number: 10943919
    Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Taro Shiokawa, Masahisa Sonoda
  • Patent number: 10865257
    Abstract: To provide a production method for an aqueous emulsion of modified polytetrafluoroethylene which is environmentally friendly and which is suitable for producing a stretched porous body having excellent breaking strength. A production method for an aqueous emulsion of modified polytetrafluoroethylene, which is a method to obtain an aqueous emulsion of modified polytetrafluoroethylene particles having an average primary particle diameter of from 0.10 to 0.30 ?m, by subjecting tetrafluoroethylene and a perfluoroalkyl ethylene to emulsion polymerization in an aqueous medium, using a polymerization initiator, in the presence of a fluorinated anionic surfactant having a LogPOW of from 2.4 to 3.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 15, 2020
    Assignee: AGC Inc.
    Inventors: Shinya Higuchi, Hiroki Nagai, Shigeki Kobayashi
  • Publication number: 20200303402
    Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.
    Type: Application
    Filed: August 2, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki KOBAYASHI, Taro SHIOKAWA, Masahisa SONODA
  • Patent number: 10622303
    Abstract: According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shigeki Kobayashi, Masaru Kito
  • Patent number: 10622373
    Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Hiroshi Nakaki
  • Publication number: 20200075625
    Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.
    Type: Application
    Filed: March 6, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shigeki KOBAYASHI, Masaru KITO, Yasuhiro UCHIYAMA
  • Publication number: 20200056031
    Abstract: To provide a PTFE aqueous dispersion which is excellent in mechanical stability, while being not susceptible to foaming. A polytetrafluoroethylene aqueous dispersion which is characterized by containing from 15 to 70 mass % of PTFE particles having an average primary particle diameter of from 0.1 to 0.5 ?m; from 0.1 to 20,000 ppm, to the PTFE particles, of a fluorinated emulsifier selected from a C4-7 fluorinated carboxylic acid which may have an etheric oxygen atom, and salts of thereof; from 1 to 20 parts by mass, to 100 parts by mass of the PTFE particles, of a nonionic surfactant represented by R1—O-A-H (wherein R1 is a C8-18 alkyl group, and A is a polyoxyalkylene chain); from 0.004 to 0.040 parts by mass, to 100 parts by mass of the PTFE particles, of a polyether polysiloxane copolymer, wherein the polyether chain consists solely of a polyoxypropylene group; and water.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Applicants: AGC INC., AGC Chemicals Europe, Limited
    Inventors: Shigeki KOBAYASHI, Masahiro Takazawa, Ariana Claudia Morgovan-Ene, Anthony Eugene Wade, Diane Caine
  • Publication number: 20190296040
    Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro FUJII, Masahisa SONODA, Masaru KITO, Satoshi NAGASHIMA, Shigeki KOBAYASHI
  • Patent number: 10353248
    Abstract: An electro-optical device includes a first substrate, a second substrate, an adhesive agent between the first and second substrates, and an inorganic film. The adhesive agent has a first face stuck to the first substrate, a second face stuck to the second substrate, and a third face between the first and second faces. The inorganic film covers the third face on one side of the electro-optical device, a region of the first substrate between the first face and a side of the first substrate on the one side, and a region of the second substrate between the second face and a side of the second substrate on the one side. A distance between the first substrate and the second substrate is less than a distance between the first face and the side of the first substrate, and a distance between the second face and the side of the second substrate.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 16, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Shinohara, Yuichi Shimizu, Shigeki Kobayashi, Takuya Miyakawa
  • Publication number: 20190172836
    Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: June 6, 2019
    Inventors: Shigeki KOBAYASHI, Hiroshi NAKAKI
  • Publication number: 20190144700
    Abstract: To provide a liquid composition whereby a resin powder can be uniformly dispersed in a resin or the like without being scattered, and a method for producing a film, a laminate or the like by using the liquid composition. The liquid composition comprises a liquid medium and a resin powder dispersed in the liquid medium, and characterized in that the average particle size of the resin powder is from 0.3 to 6 ?m, the volume-based cumulative 90% diameter of the resin powder is at most 8 ?m, and the resin powder is a resin containing a fluorinated copolymer having a specific functional group. And, the method is a method for producing a film, a laminate or the like by using the liquid composition.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: AGC Inc.
    Inventors: Tomoya HOSODA, Tatsuya Terada, Shigeki Kobayashi, Atsumi Yamabe
  • Publication number: 20190006275
    Abstract: According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion.
    Type: Application
    Filed: January 5, 2018
    Publication date: January 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shigeki KOBAYASHI, Masaru Kito
  • Patent number: 10121797
    Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Satoshi Konagai, Atsushi Konno, Kenta Yamada, Masaaki Higuchi, Masao Shingu, Soichiro Kitazaki, Yoshimasa Mikajiri
  • Patent number: 10115731
    Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Shigeki Kobayashi, Takamasa Okawa
  • Publication number: 20180298160
    Abstract: To provide a polytetrafluoroethylene aqueous dispersion which is excellent in mechanical stability, while being not susceptible to foaming. The polytetrafluoroethylene aqueous dispersion comprises: 15 to 70 mass % of polytetrafluoroethylene particles having an average primary particle size of 0.1 to 0.5 ?m; 0.1 to 20,000 ppm, to the mass of the polytetrafluoroethylene particles, of a fluorinated emulsifier selected from C4-7 fluorinated carboxylic acids which may have an ether oxygen atom, and salts thereof; 1 to 20 parts by mass, per 100 parts by mass of the PTFE particles, of a nonionic surfactant represented by R1—O-A-H (wherein R1 is a C8-18 alkyl group, and A is a polyoxyalkylene chain); 0.01 to 3.0 parts by mass, per 100 parts by mass of the polytetrafluoroethylene particles, of a compound represented by the formula (2) (wherein R is a C2-4 alkyl group, n is 1 or 2, and each of m1 and m2 is an average repeating number of oxyethylene groups, with (m1+m2) being 1 to 6); and water.
    Type: Application
    Filed: May 9, 2018
    Publication date: October 18, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki KOBAYASHI, Hiroki NAGAI, Shinya HIGUCHI, Akiko TANAKA, Masahiro TAKAZAWA, Ariana Claudia MORGOVAN-ENE, Anthony Eugene WADE, Diane CAINE
  • Publication number: 20180298131
    Abstract: To provide a method for producing a tetrafluoroethylene copolymer-containing aqueous dispersion excellent in stability against a mechanical stress.
    Type: Application
    Filed: May 11, 2018
    Publication date: October 18, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki Kobayashi, Hiroki Nagai, Shinya Higuchi, Akiko Tanaka, Masahiro Takazawa, Ariana Claudia Morgovan-Ene, Anthony Eugene Wade, Diane Caine
  • Publication number: 20180261614
    Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 13, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Shigeki KOBAYASHI, Takamasa OKAWA