Patents by Inventor Shigeki Kobayashi

Shigeki Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10353248
    Abstract: An electro-optical device includes a first substrate, a second substrate, an adhesive agent between the first and second substrates, and an inorganic film. The adhesive agent has a first face stuck to the first substrate, a second face stuck to the second substrate, and a third face between the first and second faces. The inorganic film covers the third face on one side of the electro-optical device, a region of the first substrate between the first face and a side of the first substrate on the one side, and a region of the second substrate between the second face and a side of the second substrate on the one side. A distance between the first substrate and the second substrate is less than a distance between the first face and the side of the first substrate, and a distance between the second face and the side of the second substrate.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 16, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Shinohara, Yuichi Shimizu, Shigeki Kobayashi, Takuya Miyakawa
  • Patent number: 10316776
    Abstract: A control apparatus for an internal combustion engine having an exhaust gas purification device which is arranged in an exhaust passage and includes a NOx storage reduction (NSR) catalyst. The control apparatus, when the air fuel ratio of the air-fuel mixture is shifted from a lean air fuel ratio to the stoichiometric air fuel ratio, determines a predetermined NOx amount so as to be larger when the temperature detected by the first detection unit is high in comparison with when the detected temperature is low, and when the storage amount of NOx in the NSR catalyst is larger than the predetermined NOx amount, performs the rich spike processing and then controls the air fuel ratio to the stoichiometric air fuel ratio, whereas when otherwise, controls the air fuel ratio to the stoichiometric air fuel ratio without performing the rich spike processing.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: June 11, 2019
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroshi Kobayashi, Kazuhiro Umemoto, Toshihiro Mori, Shigeki Nakayama
  • Publication number: 20190172836
    Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: June 6, 2019
    Inventors: Shigeki KOBAYASHI, Hiroshi NAKAKI
  • Patent number: 10304606
    Abstract: A coil assembly includes a coil unit in which a coil obtained by winding a winding wire is disposed around a magnetic core, a coil case that accommodates the coil unit, and a potting material with which an inside of the coil case is filled, and the coil case has an elastic fixing portion that is attachable to a resin member to which the coil case is to be fixed. The above-described configuration makes it possible to provide a coil assembly that is unlikely to crack and generate abnormal noises.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 28, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Junya Aichi, Yoshikazu Sasaki, Kyungwoo Kim, Shigeki Yamane, Takehito Kobayashi, Yukinori Kita, Tomohiro Ooi, Toru Takahashi
  • Publication number: 20190144700
    Abstract: To provide a liquid composition whereby a resin powder can be uniformly dispersed in a resin or the like without being scattered, and a method for producing a film, a laminate or the like by using the liquid composition. The liquid composition comprises a liquid medium and a resin powder dispersed in the liquid medium, and characterized in that the average particle size of the resin powder is from 0.3 to 6 ?m, the volume-based cumulative 90% diameter of the resin powder is at most 8 ?m, and the resin powder is a resin containing a fluorinated copolymer having a specific functional group. And, the method is a method for producing a film, a laminate or the like by using the liquid composition.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: AGC Inc.
    Inventors: Tomoya HOSODA, Tatsuya Terada, Shigeki Kobayashi, Atsumi Yamabe
  • Publication number: 20190006275
    Abstract: According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion.
    Type: Application
    Filed: January 5, 2018
    Publication date: January 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shigeki KOBAYASHI, Masaru Kito
  • Patent number: 10121797
    Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Satoshi Konagai, Atsushi Konno, Kenta Yamada, Masaaki Higuchi, Masao Shingu, Soichiro Kitazaki, Yoshimasa Mikajiri
  • Patent number: 10115731
    Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Shigeki Kobayashi, Takamasa Okawa
  • Publication number: 20180298131
    Abstract: To provide a method for producing a tetrafluoroethylene copolymer-containing aqueous dispersion excellent in stability against a mechanical stress.
    Type: Application
    Filed: May 11, 2018
    Publication date: October 18, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki Kobayashi, Hiroki Nagai, Shinya Higuchi, Akiko Tanaka, Masahiro Takazawa, Ariana Claudia Morgovan-Ene, Anthony Eugene Wade, Diane Caine
  • Publication number: 20180298160
    Abstract: To provide a polytetrafluoroethylene aqueous dispersion which is excellent in mechanical stability, while being not susceptible to foaming. The polytetrafluoroethylene aqueous dispersion comprises: 15 to 70 mass % of polytetrafluoroethylene particles having an average primary particle size of 0.1 to 0.5 ?m; 0.1 to 20,000 ppm, to the mass of the polytetrafluoroethylene particles, of a fluorinated emulsifier selected from C4-7 fluorinated carboxylic acids which may have an ether oxygen atom, and salts thereof; 1 to 20 parts by mass, per 100 parts by mass of the PTFE particles, of a nonionic surfactant represented by R1—O-A-H (wherein R1 is a C8-18 alkyl group, and A is a polyoxyalkylene chain); 0.01 to 3.0 parts by mass, per 100 parts by mass of the polytetrafluoroethylene particles, of a compound represented by the formula (2) (wherein R is a C2-4 alkyl group, n is 1 or 2, and each of m1 and m2 is an average repeating number of oxyethylene groups, with (m1+m2) being 1 to 6); and water.
    Type: Application
    Filed: May 9, 2018
    Publication date: October 18, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki KOBAYASHI, Hiroki NAGAI, Shinya HIGUCHI, Akiko TANAKA, Masahiro TAKAZAWA, Ariana Claudia MORGOVAN-ENE, Anthony Eugene WADE, Diane CAINE
  • Publication number: 20180261614
    Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 13, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Shigeki KOBAYASHI, Takamasa OKAWA
  • Publication number: 20180246357
    Abstract: An electro-optical device includes a first substrate, a second substrate, an adhesive agent between the first and second substrates, and an inorganic film. The adhesive agent has a first face stuck to the first substrate, a second face stuck to the second substrate, and a third face between the first and second faces. The inorganic film covers the third face on one side of the electro-optical device, a region of the first substrate between the first face and a side of the first substrate on the one side, and a region of the second substrate between the second face and a side of the second substrate on the one side. A distance between the first substrate and the second substrate is less than a distance between the first face and the side of the first substrate, and a distance between the second face and the side of the second substrate.
    Type: Application
    Filed: May 1, 2018
    Publication date: August 30, 2018
    Inventors: Takashi Shinohara, Yuichi Shimizu, Shigeki Kobayashi, Takuya Miyakawa
  • Publication number: 20180201708
    Abstract: A fluororesin excellent in radiation resistance is provided. A fluororesin composed of a tetrafluoroethylene/ethylene copolymer which is a bipolymer of tetrafluoroethylene and ethylene containing units derived from tetrafluoroethylene in a proportion of from 50 to 60 mol % relative to the total of the units derived from tetrafluoroethylene and units derived from ethylene, wherein the melt flow rate measured at a temperature of 297° C. under a load of 49 N in accordance with ASTM D3159 is 0.1 g/10 min or less.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Applicant: ASAHI GLASS COMPANY, LIMITED
    Inventors: Keisuke YAGI, Shigeki Kobayashi, Hiroki Nagai
  • Publication number: 20180194884
    Abstract: To provide a modified polytetrafluoroethylene which is excellent in the moldability by paste extrusion and the mechanical property of the molded article. A modified polytetrafluoroethylene fine powder which is a fine powder of a non-melt-moldable modified polytetrafluoroethylene, characterized in that the modified polytetrafluoroethylene comprises units derived from tetrafluoroethylene, units derived from a perfluoroalkyl vinyl ether represented by CF2?CFO—CnF2n+1 (wherein n is an integer of from 1 to 6), and units derived from a perfluoroalkylethylene represented by CH2?CH—CmF2m+1 (wherein m is an integer of from 3 to 6), and that the content of the units derived from the perfluoroalkyl vinyl ether is from 0.1 to 0.25 mass % and the content of the units derived from a perfluoroalkylethylene is from 0.001 to 0.1 mass %, based on all monomer units in the modified polytetrafluoroethylene.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki KOBAYASHI, Ariana Claudia MORGOVAN-ENE, Anthony Eugene WADE
  • Patent number: 9989810
    Abstract: An electro-optical device comprises an element substrate, a counter substrate, and an inorganic film. The counter substrate is arranged so as to face the element substrate. The seal material is arranged between the element substrate and the counter substrate so as to join the element substrate and the counter substrate. The inorganic film covers a side face of the seal material, a peripheral region of the element substrate between the side face of the seal material and a side of the element substrate, and a peripheral region of the counter substrate between the side face of the seal material and a side of the counter substrate.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: June 5, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Shinohara, Yuichi Shimizu, Shigeki Kobayashi, Takuya Miyakawa
  • Publication number: 20180142043
    Abstract: To provide a production method for an aqueous emulsion of modified polytetrafluoroethylene which is environmentally friendly and which is suitable for producing a stretched porous body having excellent breaking strength. A production method for an aqueous emulsion of modified polytetrafluoroethylene, which is a method to obtain an aqueous emulsion of modified polytetrafluoroethylene particles having an average primary particle diameter of from 0.10 to 0.30 ?m, by subjecting tetrafluoroethylene and a perfluoroalkyl ethylene to emulsion polymerization in an aqueous medium, using a polymerization initiator, in the presence of a fluorinated anionic surfactant having a LogPOW of from 2.4 to 3.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Applicant: Asahi Glass Company, Limited
    Inventors: Shinya Higuchi, Hiroki Nagai, Shigeki Kobayashi
  • Patent number: 9978770
    Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 22, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Atsushi Konno
  • Publication number: 20180037689
    Abstract: To optimize the primary particle size of a modified PTFE fine powder to shorten the sintering time during the extrusion molding. A modified polytetrafluoroethylene fine powder which is a fine powder of a non-melt-processable modified polytetrafluoroethylene comprising units derived from tetrafluoroethylene, units derived from hexafluoropropylene, units derived from a perfluoro(alkyl vinyl ether) represented by CF2?CFO—CnF2n+1 (n is an integer of from 1 to 6) and units derived from a (perfluoalkyl)ethylene represented by CH2?CH—CmF2m+1 (m is an integer of from 3 to 7).
    Type: Application
    Filed: October 20, 2017
    Publication date: February 8, 2018
    Applicants: ASAHI GLASS COMPANY, LIMITED, AGC CHEMICALS EUROPE, LIMITED
    Inventors: Shigeki KOBAYASHI, Ariana Claudia MORGOVAN-ENE, Anthony Eugene WADE
  • Patent number: 9842853
    Abstract: A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuru Sato, Shigeki Kobayashi, Tsutomu Murase
  • Patent number: 9831121
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Okawa, Shigeki Kobayashi, Kei Sakamoto, Ryosuke Sawabe