Patents by Inventor Shigeki Matsue

Shigeki Matsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4429375
    Abstract: A high speed memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.
    Type: Grant
    Filed: July 23, 1981
    Date of Patent: January 31, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Satoru Kobayashi, Shigeki Matsue
  • Patent number: 4395764
    Abstract: A memory device which is effectively utilized as serial access memory with variable shift length of stored data is disclosed. The memory device comprises memory cells arrayed in a matrix form, a shift register whose output is used for selecting memory cells and control means for varying shift length of the shift register.
    Type: Grant
    Filed: December 29, 1980
    Date of Patent: July 26, 1983
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Shigeki Matsue
  • Patent number: 3987315
    Abstract: An amplifier circuit for amplifying an input signal includes a flip-flop circuit activated by a timing signal. A trigger circuit generates a first trigger signal of the same polarity as the input signal and another circuit generates a second trigger signal of the opposite polarity to the input signal. The flip-flop circuit is triggered by the first and second trigger signals at the same time the flip-flop circuit is activated by the timing signal.
    Type: Grant
    Filed: September 3, 1975
    Date of Patent: October 19, 1976
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Shigeki Matsue
  • Patent number: 3962686
    Abstract: A memory circuit employing insulated-gate field-effect transistors includes a first circuit for generating a signal upon the completion of one of the circuit functions involved in the operation of the memory circuit. That signal is applied to a second circuit which thereupon produces a timing signal that is used to control a second circuit function of the memory circuit.
    Type: Grant
    Filed: August 9, 1974
    Date of Patent: June 8, 1976
    Assignee: Nippon Electric Company Limited
    Inventors: Shigeki Matsue, Hajime Shirato