Patents by Inventor Shigeki Ohbayashi
Shigeki Ohbayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262707Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: May 4, 2017Date of Patent: April 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Patent number: 10229721Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: May 4, 2017Date of Patent: March 12, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Publication number: 20170236579Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: ApplicationFiled: May 4, 2017Publication date: August 17, 2017Applicant: Renesas Electronics CorporationInventors: Koji NII, Shigeki OHBAYASHI, Yasumasa TSUKAMOTO, Makoto YABUUCHI
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Patent number: 9672900Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: February 24, 2016Date of Patent: June 6, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Publication number: 20160172023Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: ApplicationFiled: February 24, 2016Publication date: June 16, 2016Applicant: Renesas Electronics CorporationInventors: Koji NII, Shigeki OHBAYASHI, Yasumasa TSUKAMOTO, Makoto YABUUCHI
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Patent number: 9299418Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: April 28, 2014Date of Patent: March 29, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Patent number: 8908419Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: March 18, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Publication number: 20140293680Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: ApplicationFiled: April 28, 2014Publication date: October 2, 2014Applicant: Renesas Electronics CorporationInventors: Koji NII, Shigeki OHBAYASHI, Yasumasa TSUKAMOTO, Makoto YABUUCHI
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Patent number: 8743645Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: December 14, 2011Date of Patent: June 3, 2014Assignee: Renesas Electronics CorporationInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Publication number: 20130234256Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: March 18, 2013Publication date: September 12, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hidemoto TOMITA, Shigeki OHBAYASHI, Yoshiyuki ISHIGAKI
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Patent number: 8422274Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: November 15, 2011Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 8395932Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: June 30, 2010Date of Patent: March 12, 2013Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION
Publication number: 20120087198Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: ApplicationFiled: December 14, 2011Publication date: April 12, 2012Applicant: Renesas Electronics CorporationInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Publication number: 20120063213Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: November 15, 2011Publication date: March 15, 2012Applicant: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Semiconductor memory device with adjustable selected word line potential under low voltage condition
Patent number: 8098533Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: GrantFiled: June 25, 2009Date of Patent: January 17, 2012Assignee: Renesas Electronics CorporationInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Publication number: 20100265752Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: Renesas Technology Corp.Inventors: Hidemoto TOMITA, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Semiconductor memory device with adjustable selected work line potential under low voltage condition
Publication number: 20090268531Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: ApplicationFiled: June 25, 2009Publication date: October 29, 2009Applicant: Renesas Technology Corp.Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Patent number: 7589566Abstract: A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing charges born by the metal interconnection during a plasma process to first and second wells, and first and second MOS transistors maintaining a voltage between the first and second wells at a level not higher than a prescribed voltage. Therefore, even when an antenna ratio is high, a gate oxide film in the first and second MOS transistors is not damaged during the plasma process.Type: GrantFiled: December 1, 2005Date of Patent: September 15, 2009Assignee: Renesas Technology Corp.Inventors: Shigeki Ohbayashi, Hiroaki Suzuki, Koichiro Ishibashi, Hiroshi Makino
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Semiconductor memory device with adjustable selected work line potential under low voltage condition
Patent number: 7570525Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: GrantFiled: July 25, 2006Date of Patent: August 4, 2009Assignee: Renesas Technology Corp.Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Patent number: 7505339Abstract: A supply instruction signal attains the H-level before data is written into a plurality of memory cells. A P-channel MOS transistor is arranged between a power supply node and an input node. The P-channel MOS transistor is turned off to open the input node according to the supply instruction signal. In this case, a write driver discharges electric charges accumulated on the input node and electric charges accumulated on a bit line pair. However, a through-current does not flow from the power supply node to a ground node so that flow of the through-current to a CMOS inverter circuit forming each memory cell can be prevented. Accordingly, such a static semiconductor memory device can be provided that can prevent the flow of the through-current to the CMOS inverter circuit forming each memory cell when simultaneously writing data into the plurality of memory cells.Type: GrantFiled: June 13, 2006Date of Patent: March 17, 2009Assignee: Renesas Technology Corp.Inventor: Shigeki Ohbayashi