Abstract: In a semiconductor device and an information processing system according to one embodiment, an external device generates external device unique information by using a unique code which is a value unique to the semiconductor device, and generates second information by encrypting the first information with the use of the external device unique information. The semiconductor device stores the second information and generates the principal device unique information independently of the external device, with the use of the unique code of the semiconductor device holding the second information, and decrypts the second information with the use of the principal device unique information to obtain the first information.

Abstract: It is possible to prevent a central processing unit and a security processing unit from accessing of a non-volatile memory at the same time. A data flash 13 includes a secure area 31 and a user area 32. In the secure area 31, a plurality of pieces of security information used in a security process is stored. A security IP 12 reads out a portion of the plurality of pieces of security information from the secure area 31 and stores it in the secure RAM 22. When the security information to be used in the security process is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses it.

Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).

Abstract: In an on-vehicle system, the gateway is duplexed, and a countermeasure table is included. The countermeasure table defines a failure phenomenon occurring in communication, an identification method for identifying a factor on whether the failure phenomenon is caused by a failure of the gateway or caused by a security attack on the gateway, and a corresponding countermeasure method. When it is detected that a failure phenomenon has occurred is communication through the gateway, the on-vehicle system determines a factor of the detected failure phenomenon based on the identification method defined in the countermeasure table, and makes countermeasures in accordance with the corresponding countermeasure method.

Abstract: In a semiconductor device and an information processing system according to one embodiment, an external device generates external device unique information by using a unique code which is a value unique to the semiconductor device, and generates second information by encrypting the first information with the use of the external device unique information. The semiconductor device stores the second information and generates the principal device unique information independently of the external device, with the use of the unique code of the semiconductor device holding the second information, and decrypts the second information with the use of the principal device unique information to obtain the first information.

Abstract: It is possible to prevent a central processing unit and a security processing unit from accessing of a non-volatile memory at the same time. A data flash 13 includes a secure area 31 and a user area 32. In the secure area 31, a plurality of pieces of security information used in a security process is stored. A security IP 12 reads out a portion of the plurality of pieces of security information from the secure area 31 and stores it in the secure RAM 22. When the security information to be used in the security process is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses it.

Abstract: In a semiconductor device and an information processing system according to one embodiment, an external device generates external device unique information by using a unique code which is a value unique to the semiconductor device, and generates second information by encrypting the first information with the use of the external device unique information. The semiconductor device stores the second information and generates the principal device unique information independently of the external device, with the use of the unique code of the semiconductor device holding the second information, and decrypts the second information with the use of the principal device unique information to obtain the first information.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: In an on-vehicle system, the gateway is duplexed, and a countermeasure table is included. The countermeasure table defines a failure phenomenon occurring in communication, an identification method for identifying a factor on whether the failure phenomenon is caused by a failure of the gateway or caused by a security attack on the gateway, and a corresponding countermeasure method. When it is detected that a failure phenomenon has occurred is communication through the gateway, the on-vehicle system determines a factor of the detected failure phenomenon based on the identification method defined in the countermeasure table, and makes countermeasures in accordance with the corresponding countermeasure method.

Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).

Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).

Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).

Abstract: A semiconductor device has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.

Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.

Abstract: A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.

Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).

Abstract: A semiconductor device has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.

Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.