Patents by Inventor Shigemi Horiuchi
Shigemi Horiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945446Abstract: An in-vehicle control device includes: a requested torque calculation unit which calculates a requested torque on the basis of a driving state of a vehicle; a requested torque change amount calculation unit which calculates the amount of change in requested torque per unit time as a requested torque change amount; an estimated generation torque calculation unit which calculates estimated generation torque estimated as being generated by an engine; an estimated generation torque change amount calculation unit which calculates the amount of change in estimated generation torque per unit time as an estimated generation torque change amount; and an abnormality detection unit which detects an abnormality of the engine on the basis of the integrated value of a difference between the requested torque change amount and the estimated generation torque change amount, and outputs abnormality determination for the engine.Type: GrantFiled: November 27, 2019Date of Patent: April 2, 2024Assignee: Hitachi Astemo, Ltd.Inventors: Shigemi Oono, Sadato Horiuchi
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Patent number: 8420502Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.Type: GrantFiled: February 22, 2010Date of Patent: April 16, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Patent number: 7781241Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.Type: GrantFiled: November 29, 2007Date of Patent: August 24, 2010Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Ryohei Inazawa, Toshiya Uemura
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Publication number: 20100151612Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: TOYODA GOSEI CO., LTD.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Patent number: 7646036Abstract: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. A positive electrode is formed on a p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O). By virtue of this structure, migration of silver from the silver alloy reflecting electrode layer and blackening of the interface between the silver alloy layer and the ITO light-transmitting electrode layer disposed thereunder are prevented, whereby light extraction efficiency can be enhanced.Type: GrantFiled: February 4, 2008Date of Patent: January 12, 2010Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd.Inventors: Takahiro Kozawa, Kazuyoshi Tomita, Toshiya Uemura, Shigemi Horiuchi
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Patent number: 7541262Abstract: The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica filler particles (diameter: about 2 to about 4 ?m) are added to the base material in an appropriate amount. Charging of the second adhesive may be performed by adding the adhesive dropwise to a side wall of a semiconductor wafer, or by immersing an edge of the semiconductor wafer in the adhesive in the form of liquid. When a liquid-form epoxy material of low viscosity is employed, the spaces can be evenly filled with the second adhesive by capillary action. An n-electrode is formed on an exposed surface of an n-type layer through vapor deposition employing a resist mask. Separation trenches are formed through half-cut dicing from the exposed surface of the n-type layer toward the second adhesive.Type: GrantFiled: December 5, 2006Date of Patent: June 2, 2009Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Toshiya Uemura, Shigemi Horiuchi
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Publication number: 20080237629Abstract: A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.Type: ApplicationFiled: March 14, 2008Publication date: October 2, 2008Applicant: TOYODA GOSEI, CO., LTD.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Publication number: 20080210955Abstract: An object of the invention is to prevent short circuit at a side surface of a semiconductor device in the method for producing semiconductor devices including a laser lift-off step. The production method of the invention includes forming, on a sapphire substrate, a group III nitride semiconductor layer containing a plurality of semiconductor devices isolated from one another by a groove which reaches the substrate; forming a protective film for preventing short circuit on the top surface and side surfaces of the semiconductor layer and on the top surface of the sapphire substrate; forming a resin layer in the groove; bonding the semiconductor layer to a support substrate via a low-melting-point metal layer; and removing the sapphire substrate through the laser lift-off process. The resin layer functions as a support for the protective film, to thereby prevent cracking or chipping of the protective film.Type: ApplicationFiled: January 28, 2008Publication date: September 4, 2008Applicant: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi
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Publication number: 20080185609Abstract: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. An n-type AlxGayIn1-x-yN layer, a light-emitting layer, and a p-type AlxGayIn1-x-yN layer are formed on a dielectric substrate such as a sapphire substrate. After formation of these layers, the n-type AlxGayIn1-x-yN layer is exposed through etching or a similar technique, and an n-electrode is formed on the exposed area. A positive electrode is formed on the p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O).Type: ApplicationFiled: February 4, 2008Publication date: August 7, 2008Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYODA GOSEI CO., LTD.Inventors: Takahiro KOZAWA, Kazuyoshi TOMITA, Toshiya UEMURA, Shigemi HORIUCHI
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Publication number: 20080149953Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.Type: ApplicationFiled: November 29, 2007Publication date: June 26, 2008Applicant: TOYODA GOSEI CO., LTD.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Ryohei Inazawa, Toshiya Uemura
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Publication number: 20070138540Abstract: An object of the invention is to prevent defoliation of a first electrode layer of the device of the invention including a high-reflectance metal layer. In the group III nitride based compound semiconductor optical device of the invention, an electrode formed on a p-type layer has a first electrode layer which is formed from high-reflectance rhodium (Rh) and which is directly joined to the p-type layer, and a second electrode layer which is formed from titanium (Ti) having reactivity with nitrogen and which is provided so as to cover the first electrode layer, and a portion of the second electrode layer is joined to the uppermost layer of the group III nitride based compound semiconductor.Type: ApplicationFiled: December 5, 2006Publication date: June 21, 2007Applicant: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi, Masanobu Ando
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Publication number: 20070141753Abstract: The present invention relates to method for producing a group III nitride based compound semiconductor device, including separating the device into individual chips by means of a dicing blade. A portion of an epitaxial layer where a dicing blade is to be positioned is partially or totally removed through etching, to thereby form a trench. An insulating film is formed on the bottom and on the side surfaces of the trench. A wafer is diced into chips in such a manner that the bottom of the trench is removed by means of the dicing blade without completely removing the side surfaces of the insulating film. The insulting film is formed on the side surfaces of the trench such that the film covers a p-type layer to an n-type layer included in group III nitride based compound semiconductor layers so as to prevent short circuit between the p-type layer and the n-type layer.Type: ApplicationFiled: December 5, 2006Publication date: June 21, 2007Applicant: TOYODA GOSEI CO., LTDInventors: Toshiya Uemura, Shigemi Horiuchi
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Publication number: 20070141806Abstract: The present invention relates to method for producing a group III nitride based compound semiconductor device. A plurality of group III nitride based compound semiconductor layers are epitaxially grown on a first substrate. An electrode is formed on the uppermost layer of the group III nitride based compound semiconductor layers, the electrode being formed of a first multi-layer including at least a layer for preventing migration of tin contained in a solder. A second multi-layer including at least a layer for preventing migration of tin contained in a solder is formed on a second substrate on which a semiconductor device is to be placed. The surface of the first substrate on which the electrode has been formed is joined to the surface of the second substrate on which the multi-layer has been formed by means of a solder containing at least tin. the first substrate removed from the group III nitride based compound semiconductor layers.Type: ApplicationFiled: December 5, 2006Publication date: June 21, 2007Applicant: TOYODA GOSEI CO., LTD.Inventors: Toshiya Uemura, Shigemi Horiuchi
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Publication number: 20070141807Abstract: The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica filler particles (diameter: about 2 to about 4 ?m) are added to the base material in an appropriate amount. Charging of the second adhesive may be performed by adding the adhesive dropwise to a side wall of a semiconductor wafer, or by immersing an edge of the semiconductor wafer in the adhesive in the form of liquid. When a liquid-form epoxy material of low viscosity is employed, the spaces can be evenly filled with the second adhesive by capillary action. An n-electrode is formed on an exposed surface of an n-type layer through vapor deposition employing a resist mask. Separation trenches are formed through half-cut dicing from the exposed surface of the n-type layer toward the second adhesive.Type: ApplicationFiled: December 5, 2006Publication date: June 21, 2007Applicant: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Toshiya Uemura, Shigemi Horiuchi
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Patent number: 7109529Abstract: A flip chip type of light-emitting semiconductor device using group III nitride compound includes a thick positive electrode. The positive electrode, which is made of at least one of silver (Ag), rhodium (Rh), ruthenium (Ru), platinum (Pt) and palladium (Pd), and an alloy including at least one of these metals, is adjacent to a p-type semiconductor layer, and reflect light toward a sapphire substrate. Accordingly, a positive electrode having a high reflectivity and a low contact resistance can be obtained. A first thin-film metal layer, which is made of cobalt (Co) and nickel (Ni), or any combinations of including at least one of these metals, formed between the p-type semiconductor layer and the thick electrode, can improve an adhesion between an contact layer and the thick positive electrode. A thickness of the first thin-film metal electrode should be preferably in the range of 2 ? to 200 ?, more preferably 5 ? to 50 ?. A second thin-film metal layer made of gold (Au) can further improve the adhesion.Type: GrantFiled: June 10, 2004Date of Patent: September 19, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi
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Patent number: 7095059Abstract: The present invention provides a Group III nitride compound semiconductor device in which the amount of a current allowed to be applied on a p-type pad electrode can be increased. That is, in the Group III nitride compound semiconductor device according to the present invention, a portion of a translucent electrode coming in contact with a circumferential surface of the p-type pad electrode is formed as a thick port ion to thereby increase the area of contact between the circumferential surface and the translucent electrode to thereby increase the current allowed to be applied on the p-type pad electrode. In addition, the use of the thick portion prevents cracking from occuring between the translucent electrode and the circumferential surface of the pad electrode.Type: GrantFiled: May 6, 2001Date of Patent: August 22, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Atsuo Hirano, Shigemi Horiuchi
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Patent number: 7005684Abstract: In a flip chip type Group III nitride compound semiconductor light-emitting element, an Au layer is provided on each of a surface of a p-side electrode and a surface of an n-side electrode with interposition of a Ti layer.Type: GrantFiled: June 3, 2002Date of Patent: February 28, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi
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Patent number: 6955936Abstract: An electrode pad for a Group III nitride compound semiconductor having p-type conduction includes a triple layer structure having first, second, and third metal layers, formed on an electrode layer. A protection film with a window exposing a central portion of the third metal layer is formed by etching on the third metal layer and covers the sides of the first, second, and third metal layers. The second metal layer is made of gold (Au). The first metal layer is made of an element which has ionization potential lower than gold (Au). The third metal is made of an element which has adhesiveness to the protection film stronger than that of gold (Au). Consequently, this structure of the electrode pad improves the adhesive strength between the protection layer and the third meal layer and prevents the etching of the sides of the protection film. Furthermore, the contact resistance between the semiconductor and the electrode pad is lowered and, thus, ohmic characteristic of the electrode pad is improved.Type: GrantFiled: September 26, 2003Date of Patent: October 18, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Shigemi Horiuchi
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Patent number: 6936859Abstract: A flip chip type of light-emitting semiconductor device using group III nitride compound comprising a thick positive electrode. The positive electrode, which is made of at least one of silver (Ag), rhodium (Rh), ruthenium (Ru), platinum (Pt) and palladium (Pd), and an alloy including at least one of these metals, is adjacent to a p-type semiconductor layer, and reflect light toward a sapphire substrate. Accordingly, a positive electrode having a high reflectivity and a low contact resistance can be obtained. A first thin-film metal layer, which is made of cobalt (Co) and nickel (Ni), or any combinations of including at least one of these metals, formed between the p-type semiconductor layer and the thick electrode, can improve an adhesion between a contact layer and the thick positive electrode. A thickness of the first thin-film metal electrode should be preferably in the range of 2 ? to 200 ?, more preferably 5 ? to 50 ?. A second thin-film metal layer made of gold (Au) can further improve the adhesion.Type: GrantFiled: April 27, 2000Date of Patent: August 30, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi
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Patent number: 6867058Abstract: A transparent electrode film containing gold for covering the uppermost layer of a group III nitride semiconductor device has a first layer formed on the uppermost layer and not thicker than 15 ?, and a second layer formed on the first layer and containing gold. The first layer contains a first metal having an ionization potential lower than that of gold, and the second layer further contains a second metal having an ionization potential lower than that of gold.Type: GrantFiled: December 23, 2002Date of Patent: March 15, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Shigemi Horiuchi