Patents by Inventor Shigenari Okada

Shigenari Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257944
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: February 22, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Shigenari Okada, Masaki Nagata
  • Patent number: 11075631
    Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, and a first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. The first and second input circuits are connected in series. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: July 27, 2021
    Assignee: OMRON CORPORATION
    Inventors: Toshinobu Akutagawa, Shigenari Okada, Shinya Sasaki
  • Patent number: 11075630
    Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, a first connection line, and a first monitor terminal connected to the first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: July 27, 2021
    Assignee: OMRON CORPORATION
    Inventors: Shinya Sasaki, Toshinobu Akutagawa, Shigenari Okada
  • Publication number: 20210135669
    Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, and a first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. The first and second input circuits are connected in series. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.
    Type: Application
    Filed: October 12, 2020
    Publication date: May 6, 2021
    Inventors: Toshinobu AKUTAGAWA, Shigenari OKADA, Shinya SASAKI
  • Publication number: 20210135668
    Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, a first connection line, and a first monitor terminal connected to the first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.
    Type: Application
    Filed: October 12, 2020
    Publication date: May 6, 2021
    Inventors: Shinya SASAKI, Toshinobu AKUTAGAWA, Shigenari OKADA
  • Publication number: 20180114857
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.
    Type: Application
    Filed: April 22, 2016
    Publication date: April 26, 2018
    Inventors: Shigenari OKADA, Masaki NAGATA
  • Patent number: 9716152
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 25, 2017
    Assignees: ROHM CO., LTD., MAXPOWER SEMICONDUCTOR, INC.
    Inventors: Masaki Nagata, Shigenari Okada, Mohamed Darwish, Jun Zeng, Peter Su
  • Publication number: 20170062574
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 2, 2017
    Applicants: ROHM CO., LTD., MaxPower Semiconductor, Inc.
    Inventors: Masaki NAGATA, Shigenari OKADA, Mohamed DARWISH, Jun ZENG, Peter SU
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Publication number: 20120077321
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 29, 2012
    Inventors: SHIGENARI OKADA, TAKUYA FUTASE, YUTAKA INABA
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 7955925
    Abstract: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase
  • Patent number: 7700448
    Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: April 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takuya Futase, Keiichiro Kashihara, Shigenari Okada
  • Publication number: 20090191707
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 30, 2009
    Inventors: Shigenari OKADA, Takuya Futase, Yutaka Inaba
  • Publication number: 20090011566
    Abstract: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Shigenari Okada, Takuya Futase
  • Publication number: 20080242035
    Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.
    Type: Application
    Filed: January 15, 2008
    Publication date: October 2, 2008
    Inventors: Takuya FUTASE, Keiichiro Kashihara, Shigenari Okada