Patents by Inventor Shigenobu Maeda

Shigenobu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330981
    Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hyun-pil Noh, Choong-ho Lee, Seog-heon Ham
  • Publication number: 20160118342
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Publication number: 20160093741
    Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.
    Type: Application
    Filed: May 5, 2015
    Publication date: March 31, 2016
    Inventors: Changjae YANG, Shigenobu MAEDA, Changhwa KIM, Youngmoon CHOI
  • Publication number: 20160093398
    Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
    Type: Application
    Filed: June 29, 2015
    Publication date: March 31, 2016
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Ji-Hoon YOON
  • Publication number: 20160087098
    Abstract: Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and includes germanium. The active layer includes a first region having a first germanium concentration, and a second region on both sides of the first region. The second region has a top surface getting higher from a first portion of the second region adjacent to the first region toward a second portion of the second region far from the first region, and has a second germanium concentration less than the first germanium concentration. The gate structure is formed on the first region of the active layer. The spacer is formed on the second region of the active layer, and contacts a sidewall of the gate structure. The source/drain layer is adjacent to the second region of the active layer.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 24, 2016
    Inventors: Bin Liu, Sun-Min Kim, Shigenobu Maeda
  • Publication number: 20160086841
    Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.
    Type: Application
    Filed: May 13, 2015
    Publication date: March 24, 2016
    Inventors: SEUNGHYUN SONG, Hyeon Kyun Noh, Taeyong Kwon, Sangsu Kim, Shigenobu Maeda, Krishna Bhuwalka, Uihui Kwon, Keunho Lee, Wonsok Lee
  • Patent number: 9293701
    Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Juyoun Kim, Shigenobu Maeda, Jihoon Yoon, Sungman Lim
  • Patent number: 9276116
    Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 1, 2016
    Assignee: Samsung Elecronics Co., Ltd.
    Inventors: Shigenobu Maeda, Tsukasa Matsuda, Hidenobu Fukutome
  • Patent number: 9240481
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20160005864
    Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.
    Type: Application
    Filed: May 28, 2015
    Publication date: January 7, 2016
    Inventors: TaeYong Kwon, Shigenobu Maeda, David Seo, Jae-Hwan Lee
  • Patent number: 9230925
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Publication number: 20150380102
    Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the firs
    Type: Application
    Filed: April 2, 2015
    Publication date: December 31, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Publication number: 20150340317
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Publication number: 20150311189
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Shigenobu Maeda, Jeong-Hwan Yang
  • Publication number: 20150294979
    Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.
    Type: Application
    Filed: April 10, 2015
    Publication date: October 15, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Ji-Hoon YOON
  • Patent number: 9153664
    Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 6, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiyotaka Imai, Young-Gwon Kim, Shigenobu Maeda, Soon-Chul Hwang
  • Publication number: 20150279995
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 1, 2015
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Publication number: 20150255469
    Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.
    Type: Application
    Filed: December 18, 2014
    Publication date: September 10, 2015
    Inventors: HYUN-MIN CHOI, Shigenobu Maeda
  • Patent number: 9123811
    Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
  • Patent number: 9099469
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 4, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda