Abstract: Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.

Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.

Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.

Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fm, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.